Viewing File: <root>/src/emu/cpu/tlcs90/tlcs90.c

    1  /*************************************************************************************************************
    2  
    3      Toshiba TLCS-90 Series MCU's
    4  
    5      emulation by Luca Elia, based on the Z80 core by Juergen Buchmueller
    6  
    7  *************************************************************************************************************/
    8  
    9  #include "emu.h"
   10  #include "debugger.h"
   11  #include "tlcs90.h"
   12  
   13  enum _e_op {    UNKNOWN,    NOP,    EX,     EXX,    LD,     LDW,    LDA,    LDI,    LDIR,   LDD,    LDDR,   CPI,    CPIR,   CPD,    CPDR,   PUSH,   POP,    JP,     JR,     CALL,   CALLR,      RET,    RETI,   HALT,   DI,     EI,     SWI,    DAA,    CPL,    NEG,    LDAR,   RCF,    SCF,    CCF,    TSET,   BIT,    SET,    RES,    INC,    DEC,    INCX,   DECX,   INCW,   DECW,   ADD,    ADC,    SUB,    SBC,    AND,    XOR,    OR,     CP,     RLC,    RRC,    RL,     RR,     SLA,    SRA,    SLL,    SRL,    RLD,    RRD,    DJNZ,   MUL,    DIV     };
   14  typedef UINT8 e_op;
   15  static const char *const op_names[] =   {   "??",       "nop",  "ex",   "exx",  "ld",   "ldw",  "lda",  "ldi",  "ldir", "ldd",  "lddr", "cpi",  "cpir", "cpd",  "cpdr", "push", "pop",  "jp",   "jr",   "call", "callr",    "ret",  "reti", "halt", "di",   "ei",   "swi",  "daa",  "cpl",  "neg",  "ldar", "rcf",  "scf",  "ccf",  "tset", "bit",  "set",  "res",  "inc",  "dec",  "incx", "decx", "incw", "decw", "add",  "adc",  "sub",  "sbc",  "and",  "xor",  "or",   "cp",   "rlc",  "rrc",  "rl",   "rr",   "sla",  "sra",  "sll",  "srl",  "rld",  "rrd",  "djnz", "mul",  "div"   };
   16  
   17  enum e_mode {
   18      MODE_NONE,  MODE_BIT8,  MODE_CC,
   19      MODE_I8,    MODE_D8,    MODE_R8,
   20      MODE_I16,   MODE_D16,   MODE_R16,
   21      MODE_MI16,  MODE_MR16,  MODE_MR16D8,    MODE_MR16R8,
   22      MODE_R16D8, MODE_R16R8
   23  };
   24  ALLOW_SAVE_TYPE(e_mode); // allow save_item on a non-fundamental type
   25  
   26  typedef UINT16 e_r;
   27  
   28  struct t90_Regs
   29  {
   30      PAIR        prvpc,pc,sp,af,bc,de,hl,ix,iy;
   31      PAIR        af2,bc2,de2,hl2;
   32      UINT8       halt, after_EI;
   33      UINT16      irq_state, irq_mask;
   34      device_irq_acknowledge_callback irq_callback;
   35      legacy_cpu_device *device;
   36      address_space *program;
   37      address_space *io;
   38      int     icount;
   39      int         extra_cycles;       // extra cycles for interrupts
   40      UINT8       internal_registers[48];
   41      UINT32      ixbase,iybase;
   42  
   43      // Timers: 4 x 8-bit + 1 x 16-bit
   44      emu_timer   *timer[4+1];
   45      UINT8       timer_value[4];
   46      UINT16      timer4_value;
   47      attotime    timer_period;
   48  
   49      // Work registers
   50      e_op        op;
   51  
   52      e_mode  mode1;
   53      e_r     r1,r1b;
   54  
   55      e_mode  mode2;
   56      e_r     r2,r2b;
   57  
   58      int cyc_t,cyc_f;
   59  
   60      UINT32  addr;
   61  
   62  };
   63  
   64  INLINE t90_Regs *get_safe_token(device_t *device)
   65  {
   66      assert(device != NULL);
   67      assert(device->type() == TMP90840 ||
   68              device->type() == TMP90841 ||
   69              device->type() == TMP91640 ||
   70              device->type() == TMP91641);
   71      return (t90_Regs *)downcast<legacy_cpu_device *>(device)->token();
   72  }
   73  
   74  enum    {
   75          T90_B,  T90_C,  T90_D,  T90_E,  T90_H,  T90_L,  T90_A,
   76          T90_BC, T90_DE, T90_HL, T90_XX, T90_IX, T90_IY, T90_SP,
   77          T90_AF, T90_PC
   78  };
   79  
   80  // Regs
   81  
   82  #define B   0
   83  #define C   1
   84  #define D   2
   85  #define E   3
   86  #define H   4
   87  #define L   5
   88  #define A   6
   89  
   90  #define BC  0
   91  #define DE  1
   92  #define HL  2
   93  //          3
   94  #define IX  4
   95  #define IY  5
   96  #define SP  6
   97  
   98  #define AF  7
   99  #define AF2 8
  100  #define PC  9
  101  
  102  #define F   cpustate->af.b.l
  103  
  104  static const char *const r8_names[] =   {   "b",    "c",    "d",    "e",    "h",    "l",    "a"                             };
  105  static const char *const r16_names[]    =   {   "bc",   "de",   "hl",   "??",   "ix",   "iy",   "sp",   "af",   "af'",  "pc"    };
  106  
  107  // Condition Codes
  108  
  109  #define FLS 0x0
  110  #define LT  0x1
  111  #define LE  0x2
  112  #define ULE 0x3
  113  #define OV  0x4
  114  #define PE  0x4
  115  #define MI  0x5
  116  #define Z   0x6
  117  #define EQ  0x6
  118  #define CR  0x7
  119  #define ULT 0x7
  120  #define T   0x8
  121  #define GE  0x9
  122  #define GT  0xa
  123  #define UGT 0xb
  124  #define NOV 0xc
  125  #define PO  0xc
  126  #define PL  0xd
  127  #define NZ  0xe
  128  #define NE  0xe
  129  #define NC  0xf
  130  #define UGE 0xf
  131  
  132  #define CF  0x01
  133  #define NF  0x02
  134  #define PF  0x04
  135  #define VF  PF
  136  #define XCF 0x08
  137  #define HF  0x10
  138  #define IF  0x20
  139  #define ZF  0x40
  140  #define SF  0x80
  141  
  142  static UINT8 SZ[256];       /* zero and sign flags */
  143  static UINT8 SZ_BIT[256];   /* zero, sign and parity/overflow (=zero) flags for BIT opcode */
  144  static UINT8 SZP[256];      /* zero, sign and parity flags */
  145  static UINT8 SZHV_inc[256]; /* zero, sign, half carry and overflow flags INC r8 */
  146  static UINT8 SZHV_dec[256]; /* zero, sign, half carry and overflow flags DEC r8 */
  147  
  148  static const char *const cc_names[] =   {   "f",    "lt",   "le",   "ule",  "ov",   "mi",   "z",    "c",    "",     "ge",   "gt",   "ugt",  "nov",  "pl",   "nz",   "nc"    };
  149  
  150  // Opcodes
  151  
  152  #define OP_16 0x80
  153  
  154  
  155  
  156  
  157  
  158  #define OP(   X,CT )        cpustate->op = X;       cpustate->cyc_t = (CT*2);
  159  #define OP16( X,CT )        OP( (X)|OP_16,CT )
  160  
  161  #define OPCC(   X,CF,CT )   OP( X, CT ) cpustate->cyc_f = (CF*2);
  162  #define OPCC16( X,CF,CT )   OPCC( (X)|OP_16,CF,CT )
  163  
  164  #define BIT8( N,I )         cpustate->mode##N = MODE_BIT8;  cpustate->r##N = I;
  165  #define I8( N,I )           cpustate->mode##N = MODE_I8;        cpustate->r##N = I;
  166  #define D8( N,I )           cpustate->mode##N = MODE_D8;        cpustate->r##N = I;
  167  #define I16( N,I )          cpustate->mode##N = MODE_I16;       cpustate->r##N = I;
  168  #define D16( N,I )          cpustate->mode##N = MODE_D16;       cpustate->r##N = I;
  169  #define R8( N,R )           cpustate->mode##N = MODE_R8;        cpustate->r##N = R;
  170  #define R16( N,R )          cpustate->mode##N = MODE_R16;       cpustate->r##N = R;
  171  #define Q16( N,R )          cpustate->mode##N = MODE_R16;       cpustate->r##N = R; if (cpustate->r##N == SP) cpustate->r##N = AF;
  172  #define MI16( N,I )         cpustate->mode##N = MODE_MI16;  cpustate->r##N = I;
  173  #define MR16( N,R )         cpustate->mode##N = MODE_MR16;  cpustate->r##N = R;
  174  #define MR16D8( N,R,I )     cpustate->mode##N = MODE_MR16D8;    cpustate->r##N = R; cpustate->r##N##b = I;
  175  #define MR16R8( N,R,g )     cpustate->mode##N = MODE_MR16R8;    cpustate->r##N = R; cpustate->r##N##b = g;
  176  #define NONE( N )           cpustate->mode##N = MODE_NONE;
  177  #define CC( N,cc )          cpustate->mode##N = MODE_CC;        cpustate->r##N = cc;
  178  #define R16D8( N,R,I )      cpustate->mode##N = MODE_R16D8; cpustate->r##N = R; cpustate->r##N##b = I;
  179  #define R16R8( N,R,g )      cpustate->mode##N = MODE_R16R8; cpustate->r##N = R; cpustate->r##N##b = g;
  180  
  181  INLINE UINT8  RM8 (t90_Regs *cpustate, UINT32 a)    { return cpustate->program->read_byte( a ); }
  182  INLINE UINT16 RM16(t90_Regs *cpustate, UINT32 a)    { return RM8(cpustate,a) | (RM8( cpustate, (a+1) & 0xffff ) << 8); }
  183  
  184  INLINE void WM8 (t90_Regs *cpustate, UINT32 a, UINT8  v)    { cpustate->program->write_byte( a, v ); }
  185  INLINE void WM16(t90_Regs *cpustate, UINT32 a, UINT16 v)    { WM8(cpustate,a,v);    WM8( cpustate, (a+1) & 0xffff, v >> 8); }
  186  
  187  INLINE UINT8  RX8 (t90_Regs *cpustate, UINT32 a, UINT32 base)   { return cpustate->program->read_byte( base | a ); }
  188  INLINE UINT16 RX16(t90_Regs *cpustate, UINT32 a, UINT32 base)   { return RX8(cpustate,a,base) | (RX8( cpustate, (a+1) & 0xffff, base ) << 8); }
  189  
  190  INLINE void WX8 (t90_Regs *cpustate, UINT32 a, UINT8  v, UINT32 base)   { cpustate->program->write_byte( base | a, v ); }
  191  INLINE void WX16(t90_Regs *cpustate, UINT32 a, UINT16 v, UINT32 base)   { WX8(cpustate,a,v,base);   WX8( cpustate, (a+1) & 0xffff, v >> 8, base); }
  192  
  193  INLINE UINT8  READ8(t90_Regs *cpustate) { UINT8 b0 = RM8( cpustate, cpustate->addr++ ); cpustate->addr &= 0xffff; return b0; }
  194  INLINE UINT16 READ16(t90_Regs *cpustate)    { UINT8 b0 = READ8(cpustate); return b0 | (READ8(cpustate) << 8); }
  195  
  196  static void decode(t90_Regs *cpustate)
  197  {
  198      UINT8  b0, b1, b2, b3;
  199      UINT16 imm16;
  200  
  201      b0 = READ8(cpustate);
  202  
  203      switch ( b0 )
  204      {
  205          case 0x00:
  206              OP( NOP,2 )         NONE( 1 )                   NONE( 2 )                       return;     // NOP
  207  
  208          case 0x01:
  209              OP( HALT,4 )        NONE( 1 )                   NONE( 2 )                       return;     // HALT
  210          case 0x02:
  211              OP( DI,2 )          NONE( 1 )                   NONE( 2 )                       return;     // DI
  212          case 0x03:
  213              OP( EI,2 )          NONE( 1 )                   NONE( 2 )                       return;     // EI
  214  
  215          case 0x07:
  216              OPCC( INCX,6,10 )   MI16( 1, 0xFF00|READ8(cpustate) )   NONE( 2 )                       return;     // INCX ($FF00+n)
  217  
  218          case 0x08:
  219              OP( EX,2 )          R16( 1, DE )                R16( 2, HL )                    return;     // EX DE,HL
  220          case 0x09:
  221              OP( EX,2 )          R16( 1, AF )                R16( 2, AF2 )                   return;     // EX AF,AF'
  222          case 0x0a:
  223              OP( EXX,2 )         NONE( 1 )                   NONE( 2 )                       return;     // EXX
  224  
  225          case 0x0b:
  226              OP( DAA,4 )         R8( 1, A )                  NONE( 2 )                       return;     // DAA A
  227  
  228          case 0x0c:
  229              OP( RCF,2 )         NONE( 1 )                   NONE( 2 )                       return;     // RCF
  230          case 0x0d:
  231              OP( SCF,2 )         NONE( 1 )                   NONE( 2 )                       return;     // SCF
  232          case 0x0e:
  233              OP( CCF,2 )         NONE( 1 )                   NONE( 2 )                       return;     // CCF
  234  
  235          case 0x0f:
  236              OPCC( DECX,6,10 )   MI16( 1, 0xFF00|READ8(cpustate) )   NONE( 2 )                       return;     // DECX ($FF00+n)
  237  
  238          case 0x10:
  239              OP( CPL,2 )         R8( 1, A )                  NONE( 2 )                       return;     // CPL A
  240          case 0x11:
  241              OP( NEG,2 )         R8( 1, A )                  NONE( 2 )                       return;     // NEG A
  242  
  243          case 0x12:                                                                                      // MUL HL,n
  244          case 0x13:                                                                                      // DIV HL,n
  245              OP( MUL+b0-0x12,16) R16( 1, HL )                I8( 2, READ8(cpustate) )                return;
  246  
  247          case 0x14:  case 0x15:  case 0x16:
  248              OP16( ADD,6 )       R16( 1, IX+b0-0x14 )        I16( 2, READ16(cpustate) )              return;     // ADD ix,mn
  249  
  250          case 0x17:
  251              OP( LDAR,8 )        R16( 1, HL )                D16( 2, READ16(cpustate) )              return;     // LDAR HL,+cd
  252  
  253          case 0x18:
  254              OP( DJNZ,10 )       D8( 1, READ8(cpustate) )            NONE( 2 )                       return;     // DJNZ +d
  255          case 0x19:
  256              OP16( DJNZ,10 )     R16( 1, BC )                D8( 2, READ8(cpustate) )                return;     // DJNZ BC,+d
  257  
  258          case 0x1a:
  259              OPCC( JP,8,8 )      CC( 1, T )                  I16( 2, READ16(cpustate) )              return;     // JP T,mn
  260          case 0x1b:
  261              OPCC16( JR,10,10 )  CC( 1, T )                  D16( 2, READ16(cpustate) )              return;     // JR T,+cd
  262  
  263          case 0x1c:
  264              OPCC( CALL,14,14 )  CC( 1, T )                  I16( 2, READ16(cpustate) )              return;     // CALL T,mn
  265          case 0x1d:
  266              OP( CALLR,16 )      D16( 1, READ16(cpustate) )          NONE( 2 )                       return;     // CALLR +cd
  267  
  268          case 0x1e:
  269              OPCC( RET,10,10 )   CC( 1, T )                  NONE( 2 )                       return;     // RET T
  270          case 0x1f:
  271              OP( RETI,14 )       NONE( 1 )                   NONE( 2 )                       return;     // RETI
  272  
  273          case 0x20:  case 0x21:  case 0x22:  case 0x23:  case 0x24:  case 0x25:  case 0x26:
  274              OP( LD,2 )          R8( 1, A )                  R8( 2, b0 - 0x20 )              return;     // LD A,r
  275  
  276          case 0x27:
  277              OP( LD,8 )          R8( 1, A )                  MI16( 2, 0xFF00|READ8(cpustate) )       return;     // LD A,($FF00+n)
  278  
  279          case 0x28:  case 0x29:  case 0x2a:  case 0x2b:  case 0x2c:  case 0x2d:  case 0x2e:
  280              OP( LD,2 )          R8( 1, b0 - 0x28 )          R8( 2, A )                      return;     // LD r,A
  281  
  282          case 0x2f:
  283              OP( LD,8 )          MI16( 1, 0xFF00|READ8(cpustate) )   R8( 2, A )                      return;     // LD ($FF00+n), A
  284  
  285          case 0x30:  case 0x31:  case 0x32:  case 0x33:  case 0x34:  case 0x35:  case 0x36:
  286              OP( LD,4 )          R8( 1, b0 - 0x30 )          I8( 2, READ8(cpustate) )                return;     // LD r,n
  287  
  288          case 0x37:
  289              OP( LD,10 )         MI16( 1, 0xFF00|READ8(cpustate) )   I8( 2, READ8(cpustate) )                return;     // LD ($FF00+w),n
  290  
  291          case 0x38:  case 0x39:  case 0x3a:  /*case 0x3b:*/  case 0x3c:  case 0x3d:  case 0x3e:
  292              OP16( LD,6 )        R16( 1, b0 - 0x38 )         I16( 2, READ16(cpustate) )              return;     // LD rr,nn
  293  
  294          case 0x3f:
  295              OP( LDW,14 )        MI16( 1, 0xFF00|READ8(cpustate) )   I16( 2, READ16(cpustate) )              return;     // LDW ($FF00+w),mn
  296  
  297          case 0x40:  case 0x41:  case 0x42:  /*case 0x43:*/  case 0x44:  case 0x45:  case 0x46:
  298              OP16( LD,4 )        R16( 1, HL )                R16( 2, b0 - 0x40 )             return;     // LD HL,rr
  299  
  300          case 0x47:
  301              OP16( LD,10 )       R16( 1, HL )                MI16( 2, 0xFF00|READ8(cpustate) )       return;     // LD HL,($FF00+n)
  302  
  303          case 0x48:  case 0x49:  case 0x4a:  /*case 0x4b:*/  case 0x4c:  case 0x4d:  case 0x4e:
  304              OP16( LD,4 )        R16( 1, b0 - 0x48 )         R16( 2, HL )                    return;     // LD rr,HL
  305  
  306          case 0x4f:
  307              OP16( LD,10 )       MI16( 1, 0xFF00|READ8(cpustate) )   R16( 2, HL )                    return;     // LD ($FF00+n), HL
  308  
  309          case 0x50:  case 0x51:  case 0x52:  /*case 0x53:*/  case 0x54:  case 0x55:  case 0x56:
  310              OP( PUSH,8 )        Q16( 1, b0 - 0x50 )         NONE( 2 )                       return;     // PUSH qq
  311          case 0x58:  case 0x59:  case 0x5a:  /*case 0x5b:*/  case 0x5c:  case 0x5d:  case 0x5e:
  312              OP( POP,10 )        Q16( 1, b0 - 0x58 )         NONE( 2 )                       return;     // POP qq
  313  
  314          case 0x60:                                                                                      // ADD A,($FF00+n)
  315          case 0x61:                                                                                      // ADC A,($FF00+n)
  316          case 0x62:                                                                                      // SUB A,($FF00+n)
  317          case 0x63:                                                                                      // SBC A,($FF00+n)
  318          case 0x64:                                                                                      // AND A,($FF00+n)
  319          case 0x65:                                                                                      // XOR A,($FF00+n)
  320          case 0x66:                                                                                      // OR  A,($FF00+n)
  321          case 0x67:                                                                                      // CP  A,($FF00+n)
  322              OP( ADD+b0-0x60,8 ) R8( 1, A )                  MI16( 2, 0xFF00|READ8(cpustate) )       return;
  323  
  324          case 0x68:                                                                                      // ADD A,n
  325          case 0x69:                                                                                      // ADC A,n
  326          case 0x6a:                                                                                      // SUB A,n
  327          case 0x6b:                                                                                      // SBC A,n
  328          case 0x6c:                                                                                      // AND A,n
  329          case 0x6d:                                                                                      // XOR A,n
  330          case 0x6e:                                                                                      // OR  A,n
  331          case 0x6f:                                                                                      // CP  A,n
  332              OP( ADD+b0-0x68,4 ) R8( 1, A )                  I8( 2, READ8(cpustate) )                return;
  333  
  334          case 0x70:                                                                                      // ADD HL,($FF00+n)
  335          case 0x71:                                                                                      // ADC HL,($FF00+n)
  336          case 0x72:                                                                                      // SUB HL,($FF00+n)
  337          case 0x73:                                                                                      // SBC HL,($FF00+n)
  338          case 0x74:                                                                                      // AND HL,($FF00+n)
  339          case 0x75:                                                                                      // XOR HL,($FF00+n)
  340          case 0x76:                                                                                      // OR  HL,($FF00+n)
  341          case 0x77:                                                                                      // CP  HL,($FF00+n)
  342              OP16( ADD+b0-0x70,10 )  R16( 1, HL )            MI16( 2, 0xFF00|READ8(cpustate) )       return;
  343  
  344          case 0x78:                                                                                      // ADD HL,mn
  345          case 0x79:                                                                                      // ADC HL,mn
  346          case 0x7a:                                                                                      // SUB HL,mn
  347          case 0x7b:                                                                                      // SBC HL,mn
  348          case 0x7c:                                                                                      // AND HL,mn
  349          case 0x7d:                                                                                      // XOR HL,mn
  350          case 0x7e:                                                                                      // OR  HL,mn
  351          case 0x7f:                                                                                      // CP  HL,mn
  352              OP16( ADD+b0-0x78,6 )   R16( 1, HL )            I16( 2, READ16(cpustate) )              return;
  353  
  354          case 0x80:  case 0x81:  case 0x82:  case 0x83:  case 0x84:  case 0x85:  case 0x86:
  355              OP( INC,2 )         R8( 1, b0 - 0x80 )          NONE( 2 )                       return;     // INC r
  356          case 0x87:
  357              OP( INC,10 )        MI16( 1, 0xFF00|READ8(cpustate) )   NONE( 2 )                       return;     // INC ($FF00+n)
  358  
  359          case 0x88:  case 0x89:  case 0x8a:  case 0x8b:  case 0x8c:  case 0x8d:  case 0x8e:
  360              OP( DEC,2 )         R8( 1, b0 - 0x88 )          NONE( 2 )                       return;     // DEC r
  361          case 0x8f:
  362              OP( DEC,10 )        MI16( 1, 0xFF00|READ8(cpustate) )   NONE( 2 )                       return;     // DEC ($FF00+n)
  363  
  364          case 0x90:  case 0x91:  case 0x92:  /*case 0x93:*/  case 0x94:  case 0x95:  case 0x96:
  365              OP16( INC,4 )       R16( 1, b0 - 0x90 )         NONE( 2 )                       return;     // INC rr
  366          case 0x97:
  367              OP( INCW,14 )       MI16( 1, 0xFF00|READ8(cpustate) )   NONE( 2 )                       return;     // INCW ($FF00+n)
  368          case 0x98:  case 0x99:  case 0x9a:  /*case 0x9b:*/  case 0x9c:  case 0x9d:  case 0x9e:
  369              OP16( DEC,4 )       R16( 1, b0 - 0x98 )         NONE( 2 )                       return;     // DEC rr
  370          case 0x9f:
  371              OP( DECW,14 )       MI16( 1, 0xFF00|READ8(cpustate) )   NONE( 2 )                       return;     // DECW ($FF00+n)
  372  
  373          case 0xa0:                                                                                      // RLC A
  374          case 0xa1:                                                                                      // RRC A
  375          case 0xa2:                                                                                      // RL  A
  376          case 0xa3:                                                                                      // RR  A
  377          case 0xa4:                                                                                      // SLA A
  378          case 0xa5:                                                                                      // SRA A
  379          case 0xa6:                                                                                      // SLL A
  380          case 0xa7:                                                                                      // SRL A
  381              OP( RLC+b0-0xa0,2 ) R8( 1, A )                  NONE( 2 )                       return;
  382  
  383          case 0xa8:  case 0xa9:  case 0xaa:  case 0xab:  case 0xac:  case 0xad:  case 0xae:  case 0xaf:
  384              OP( BIT,8 )         BIT8( 1, b0 - 0xa8 )        MI16( 2, 0xFF00|READ8(cpustate) )       return;     // BIT b,($FF00+n)
  385          case 0xb0:  case 0xb1:  case 0xb2:  case 0xb3:  case 0xb4:  case 0xb5:  case 0xb6:  case 0xb7:
  386              OP( RES,12 )        BIT8( 1, b0 - 0xb0 )        MI16( 2, 0xFF00|READ8(cpustate) )       return;     // RES b,($FF00+n)
  387          case 0xb8:  case 0xb9:  case 0xba:  case 0xbb:  case 0xbc:  case 0xbd:  case 0xbe:  case 0xbf:
  388              OP( SET,12 )        BIT8( 1, b0 - 0xb8 )        MI16( 2, 0xFF00|READ8(cpustate) )       return;     // SET b,($FF00+n)
  389  
  390          case 0xc0:  case 0xc1:  case 0xc2:  case 0xc3:  case 0xc4:  case 0xc5:  case 0xc6:  case 0xc7:
  391          case 0xc8:  case 0xc9:  case 0xca:  case 0xcb:  case 0xcc:  case 0xcd:  case 0xce:  case 0xcf:
  392              OPCC( JR,4,8 )      CC( 1, b0 - 0xc0 )          D8( 2, READ8(cpustate) )                return;     // JR cc,+d
  393  
  394          case 0xe0:  case 0xe1:  case 0xe2:  /*case 0xe3:*/  case 0xe4:  case 0xe5:  case 0xe6:
  395              b1 = READ8(cpustate);
  396              switch ( b1 )   {
  397                  case 0x10:                                                                              // RLD (gg)
  398                  case 0x11:                                                                              // RRD (gg)
  399                      OP( RLD+b1-0x10,12 )    MR16( 1, b0 - 0xe0 )    NONE( 2 )               return;
  400  
  401                  case 0x12:                                                                              // MUL HL,(gg)
  402                  case 0x13:                                                                              // DIV HL,(gg)
  403                      OP( MUL+b1-0x12,18 )    R16( 1, HL )            MR16( 2, b0 - 0xe0 )    return;
  404  
  405                  case 0x14:  case 0x15:  case 0x16:
  406                      OP16( ADD,8 )           R16( 1, IX+b1-0x14 )    MR16( 2, b0 - 0xe0 )    return;     // ADD ix,(gg)
  407  
  408                  case 0x28:  case 0x29:  case 0x2a:  case 0x2b:  case 0x2c:  case 0x2d:  case 0x2e:
  409                      OP( LD,6 )              R8( 1, b1 - 0x28 )      MR16( 2, b0 - 0xe0 )    return;     // LD r,(gg)
  410                  case 0x48:  case 0x49:  case 0x4a:  /*case 0x4b:*/  case 0x4c:  case 0x4d:  case 0x4e:
  411                      OP16( LD,8 )            R16( 1, b1 - 0x48 )     MR16( 2, b0 - 0xe0 )    return;     // LD rr,(gg)
  412  
  413                  case 0x50:  case 0x51:  case 0x52:  /*case 0x53:*/  case 0x54:  case 0x55:  case 0x56:
  414                      OP( EX,14 )             MR16( 1, b0 - 0xe0 )    R16( 2, b1 - 0x50 )     return;     // EX (gg),rr
  415  
  416                  case 0x60:                                                                              // ADD A,(gg)
  417                  case 0x61:                                                                              // ADC A,(gg)
  418                  case 0x62:                                                                              // SUB A,(gg)
  419                  case 0x63:                                                                              // SBC A,(gg)
  420                  case 0x64:                                                                              // AND A,(gg)
  421                  case 0x65:                                                                              // XOR A,(gg)
  422                  case 0x66:                                                                              // OR  A,(gg)
  423                  case 0x67:                                                                              // CP  A,(gg)
  424                      OP( ADD+b1-0x60,6 )     R8( 1, A )              MR16( 2, b0 - 0xe0 )    return;
  425  
  426                  case 0x70:                                                                              // ADD HL,(gg)
  427                  case 0x71:                                                                              // ADC HL,(gg)
  428                  case 0x72:                                                                              // SUB HL,(gg)
  429                  case 0x73:                                                                              // SBC HL,(gg)
  430                  case 0x74:                                                                              // AND HL,(gg)
  431                  case 0x75:                                                                              // XOR HL,(gg)
  432                  case 0x76:                                                                              // OR  HL,(gg)
  433                  case 0x77:                                                                              // CP  HL,(gg)
  434                      OP16( ADD+b1-0x70,8 )   R16( 1, HL )            MR16( 2, b0 - 0xe0 )    return;
  435  
  436                  case 0x87:
  437                      OP( INC,8 )             MR16( 1, b0 - 0xe0 )    NONE( 2 )               return;     // INC (gg)
  438                  case 0x8f:
  439                      OP( DEC,8 )             MR16( 1, b0 - 0xe0 )    NONE( 2 )               return;     // DEC (gg)
  440  
  441                  case 0x97:
  442                      OP( INCW,12 )           MR16( 1, b0 - 0xe0 )    NONE( 2 )               return;     // INCW (gg)
  443                  case 0x9f:
  444                      OP( DECW,12 )           MR16( 1, b0 - 0xe0 )    NONE( 2 )               return;     // DECW (gg)
  445  
  446                  case 0xa0:                                                                              // RLC (gg)
  447                  case 0xa1:                                                                              // RRC (gg)
  448                  case 0xa2:                                                                              // RL  (gg)
  449                  case 0xa3:                                                                              // RR  (gg)
  450                  case 0xa4:                                                                              // SLA (gg)
  451                  case 0xa5:                                                                              // SRA (gg)
  452                  case 0xa6:                                                                              // SLL (gg)
  453                  case 0xa7:                                                                              // SRL (gg)
  454                      OP( RLC+b1-0xa0,8 )     MR16( 1, b0 - 0xe0 )    NONE( 2 )               return;
  455  
  456                  case 0x18:  case 0x19:  case 0x1a:  case 0x1b:  case 0x1c:  case 0x1d:  case 0x1e:  case 0x1f:
  457                      OP( TSET,12 )           BIT8( 1, b1 - 0x18 )    MR16( 2, b0 - 0xe0 )    return;     // TSET b,(gg)
  458                  case 0xa8:  case 0xa9:  case 0xaa:  case 0xab:  case 0xac:  case 0xad:  case 0xae:  case 0xaf:
  459                      OP( BIT,6 )             BIT8( 1, b1 - 0xa8 )    MR16( 2, b0 - 0xe0 )    return;     // BIT b,(gg)
  460                  case 0xb0:  case 0xb1:  case 0xb2:  case 0xb3:  case 0xb4:  case 0xb5:  case 0xb6:  case 0xb7:
  461                      OP( RES,10 )            BIT8( 1, b1 - 0xb0 )    MR16( 2, b0 - 0xe0 )    return;     // RES b,(gg)
  462                  case 0xb8:  case 0xb9:  case 0xba:  case 0xbb:  case 0xbc:  case 0xbd:  case 0xbe:  case 0xbf:
  463                      OP( SET,10 )            BIT8( 1, b1 - 0xb8 )    MR16( 2, b0 - 0xe0 )    return;     // SET b,(gg)
  464              }   break;
  465          case 0xe3:
  466              imm16 = READ16(cpustate);
  467              b3 = READ8(cpustate);
  468              switch ( b3 )   {
  469                  case 0x10:                                                                              // RLD (mn)
  470                  case 0x11:                                                                              // RRD (mn)
  471                      OP( RLD+b3-0x10,16 )    MI16( 1, imm16 )        NONE( 2 )               return;
  472  
  473                  case 0x12:                                                                              // MUL HL,(mn)
  474                  case 0x13:                                                                              // DIV HL,(mn)
  475                      OP( MUL+b3-0x12,22 )    R16( 1, HL )            MI16( 2, imm16 )        return;
  476  
  477                  case 0x14:  case 0x15:  case 0x16:
  478                      OP16( ADD,12 )          R16( 1, IX+b3-0x14 )    MI16( 2, imm16 )        return;     // ADD ix,(mn)
  479  
  480                  case 0x28:  case 0x29:  case 0x2a:  case 0x2b:  case 0x2c:  case 0x2d:  case 0x2e:
  481                      OP( LD,10 )             R8( 1, b3 - 0x28 )      MI16( 2, imm16 )        return;     // LD r,(mn)
  482                  case 0x48:  case 0x49:  case 0x4a:  /*case 0x4b:*/  case 0x4c:  case 0x4d:  case 0x4e:
  483                      OP16( LD,12 )           R16( 1, b3 - 0x48 )     MI16( 2, imm16 )        return;     // LD rr,(mn)
  484  
  485                  case 0x50:  case 0x51:  case 0x52:  /*case 0x53:*/  case 0x54:  case 0x55:  case 0x56:
  486                      OP( EX,18 )             MI16( 1, imm16 )        R16( 2, b3 - 0x50 )     return;     // EX (mn),rr
  487  
  488                  case 0x60:                                                                              // ADD A,(mn)
  489                  case 0x61:                                                                              // ADC A,(mn)
  490                  case 0x62:                                                                              // SUB A,(mn)
  491                  case 0x63:                                                                              // SBC A,(mn)
  492                  case 0x64:                                                                              // AND A,(mn)
  493                  case 0x65:                                                                              // XOR A,(mn)
  494                  case 0x66:                                                                              // OR  A,(mn)
  495                  case 0x67:                                                                              // CP  A,(mn)
  496                      OP( ADD+b3-0x60,10 )    R8( 1, A )              MI16( 2, imm16 )        return;
  497  
  498                  case 0x70:                                                                              // ADD HL,(mn)
  499                  case 0x71:                                                                              // ADC HL,(mn)
  500                  case 0x72:                                                                              // SUB HL,(mn)
  501                  case 0x73:                                                                              // SBC HL,(mn)
  502                  case 0x74:                                                                              // AND HL,(mn)
  503                  case 0x75:                                                                              // XOR HL,(mn)
  504                  case 0x76:                                                                              // OR  HL,(mn)
  505                  case 0x77:                                                                              // CP  HL,(mn)
  506                      OP16( ADD+b3-0x70,12 )  R16( 1, HL )            MI16( 2, imm16 )        return;
  507  
  508                  case 0x87:
  509                      OP( INC,12 )            MI16( 1, imm16 )        NONE( 2 )               return;     // INC (mn)
  510                  case 0x8f:
  511                      OP( DEC,12 )            MI16( 1, imm16 )        NONE( 2 )               return;     // DEC (mn)
  512  
  513                  case 0x97:
  514                      OP( INCW,16 )           MI16( 1, imm16 )        NONE( 2 )               return;     // INCW (mn)
  515                  case 0x9f:
  516                      OP( DECW,16 )           MI16( 1, imm16 )        NONE( 2 )               return;     // DECW (mn)
  517  
  518                  case 0xa0:                                                                              // RLC (mn)
  519                  case 0xa1:                                                                              // RRC (mn)
  520                  case 0xa2:                                                                              // RL  (mn)
  521                  case 0xa3:                                                                              // RR  (mn)
  522                  case 0xa4:                                                                              // SLA (mn)
  523                  case 0xa5:                                                                              // SRA (mn)
  524                  case 0xa6:                                                                              // SLL (mn)
  525                  case 0xa7:                                                                              // SRL (mn)
  526                      OP( RLC+b3-0xa0,12 )    MI16( 1, imm16 )        NONE( 2 )               return;
  527  
  528                  case 0x18:  case 0x19:  case 0x1a:  case 0x1b:  case 0x1c:  case 0x1d:  case 0x1e:  case 0x1f:
  529                      OP( TSET,16 )           BIT8( 1, b3 - 0x18 )    MI16( 2, imm16 )        return;     // TSET b,(mn)
  530                  case 0xa8:  case 0xa9:  case 0xaa:  case 0xab:  case 0xac:  case 0xad:  case 0xae:  case 0xaf:
  531                      OP( BIT,10 )            BIT8( 1, b3 - 0xa8 )    MI16( 2, imm16 )        return;     // BIT b,(mn)
  532                  case 0xb0:  case 0xb1:  case 0xb2:  case 0xb3:  case 0xb4:  case 0xb5:  case 0xb6:  case 0xb7:
  533                      OP( RES,14 )            BIT8( 1, b3 - 0xb0 )    MI16( 2, imm16 )        return;     // RES b,(mn)
  534                  case 0xb8:  case 0xb9:  case 0xba:  case 0xbb:  case 0xbc:  case 0xbd:  case 0xbe:  case 0xbf:
  535                      OP( SET,14 )            BIT8( 1, b3 - 0xb8 )    MI16( 2, imm16 )        return;     // SET b,(mn)
  536              }   break;
  537  
  538          case 0xe7:
  539              b1 = READ8(cpustate);
  540              b2 = READ8(cpustate);
  541              switch ( b2 )   {
  542                  case 0x10:                                                                              // RLD ($FF00+n)
  543                  case 0x11:                                                                              // RRD ($FF00+n)
  544                      OP( RLD+b2-0x10,14 )    MI16( 1, 0xFF00|b1 )    NONE( 2 )               return;
  545  
  546                  case 0x12:                                                                              // MUL HL,($FF00+n)
  547                  case 0x13:                                                                              // DIV HL,($FF00+n)
  548                      OP( MUL+b2-0x12,20 )    R16( 1, HL )            MI16( 2, 0xFF00|b1 )    return;
  549  
  550                  case 0x14:  case 0x15:  case 0x16:
  551                      OP16( ADD,10 )          R16( 1, IX+b2-0x14 )    MI16( 2, 0xFF00|b1 )    return;     // ADD ix,($FF00+n)
  552  
  553                  case 0x18:  case 0x19:  case 0x1a:  case 0x1b:  case 0x1c:  case 0x1d:  case 0x1e:  case 0x1f:
  554                      OP( TSET,14 )           BIT8( 1, b2 - 0x18 )    MI16( 2, 0xFF00|b1 )    return;     // TSET b,($FF00+n)
  555                  case 0x28:  case 0x29:  case 0x2a:  case 0x2b:  case 0x2c:  case 0x2d:  case 0x2e:
  556                      OP( LD,8 )              R8( 1, b2 - 0x28 )      MI16( 2, 0xFF00|b1 )    return;     // LD r,($FF00+n)
  557                  case 0x48:  case 0x49:  case 0x4a:  /*case 0x4b:*/  case 0x4c:  case 0x4d:  case 0x4e:
  558                      OP16( LD,10 )           R16( 1, b2 - 0x48 )     MI16( 2, 0xFF00|b1 )    return;     // LD rr,($FF00+n)
  559  
  560                  case 0x50:  case 0x51:  case 0x52:  /*case 0x53:*/  case 0x54:  case 0x55:  case 0x56:
  561                      OP( EX,16 )             MI16( 1, 0xFF00|b1 )    R16( 2, b2 - 0x50 )     return;     // EX ($FF00+n),rr
  562  
  563                  case 0xa0:                                                                              // RLC ($FF00+n)
  564                  case 0xa1:                                                                              // RRC ($FF00+n)
  565                  case 0xa2:                                                                              // RL  ($FF00+n)
  566                  case 0xa3:                                                                              // RR  ($FF00+n)
  567                  case 0xa4:                                                                              // SLA ($FF00+n)
  568                  case 0xa5:                                                                              // SRA ($FF00+n)
  569                  case 0xa6:                                                                              // SLL ($FF00+n)
  570                  case 0xa7:                                                                              // SRL ($FF00+n)
  571                      OP( RLC+b2-0xa0,10 )    MI16( 1, 0xFF00|b1 )    NONE( 2 )               return;
  572              }   break;
  573  
  574          case 0xe8:  case 0xe9:  case 0xea:  /*case 0xeb:*/  case 0xec:  case 0xed:  case 0xee:
  575              b1 = READ8(cpustate);
  576              switch ( b1 )   {
  577                  case 0x20:  case 0x21:  case 0x22:  case 0x23:  case 0x24:  case 0x25:  case 0x26:
  578                      OP( LD,6 )              MR16( 1, b0 - 0xe8 )    R8( 2, b1 - 0x20 )      return;     // LD (gg),r
  579                  case 0x37:
  580                      OP( LD,8 )              MR16( 1, b0 - 0xe8 )    I8( 2, READ8(cpustate) )        return;     // LD (gg),n
  581                  case 0x3f:
  582                      OP( LDW,12 )            MR16( 1, b0 - 0xe8 )    I16( 2, READ16(cpustate) )      return;     // LDW (gg),mn
  583                  case 0x40:  case 0x41:  case 0x42:  /*case 0x43:*/  case 0x44:  case 0x45:  case 0x46:
  584                      OP16( LD,8 )            MR16( 1, b0 - 0xe8 )    R16( 2, b1 - 0x40 )     return;     // LD (gg),rr
  585  
  586                  case 0x68:                                                                              // ADD (gg),n
  587                  case 0x69:                                                                              // ADC (gg),n
  588                  case 0x6a:                                                                              // SUB (gg),n
  589                  case 0x6b:                                                                              // SBC (gg),n
  590                  case 0x6c:                                                                              // AND (gg),n
  591                  case 0x6d:                                                                              // XOR (gg),n
  592                  case 0x6e:                                                                              // OR  (gg),n
  593                      OP( ADD+b1-0x68,10 )    MR16( 1, b0 - 0xe8 )    I8( 2, READ8(cpustate) )        return;
  594                  case 0x6f:                                                                              // CP  (gg),n
  595                      OP( CP,8 )              MR16( 1, b0 - 0xe8 )    I8( 2, READ8(cpustate) )        return;
  596  
  597                  case 0xc0:  case 0xc1:  case 0xc2:  case 0xc3:  case 0xc4:  case 0xc5:  case 0xc6:  case 0xc7:
  598                  case 0xc8:  case 0xc9:  case 0xca:  case 0xcb:  case 0xcc:  case 0xcd:  case 0xce:  case 0xcf:
  599                      OPCC( JP,6,8 )          CC( 1, b1 - 0xc0 )      R16( 2, b0 - 0xe8 )     return;     // JP [cc,]gg
  600                  case 0xd0:  case 0xd1:  case 0xd2:  case 0xd3:  case 0xd4:  case 0xd5:  case 0xd6:  case 0xd7:
  601                  case 0xd8:  case 0xd9:  case 0xda:  case 0xdb:  case 0xdc:  case 0xdd:  case 0xde:  case 0xdf:
  602                      OPCC( CALL,6,14 )       CC( 1, b1 - 0xd0 )      R16( 2, b0 - 0xe8 )     return;     // CALL [cc,]gg
  603              }   break;
  604          case 0xeb:
  605              imm16 = READ16(cpustate);
  606              b3 = READ8(cpustate);
  607              switch ( b3 )   {
  608                  case 0x20:  case 0x21:  case 0x22:  case 0x23:  case 0x24:  case 0x25:  case 0x26:
  609                      OP( LD,10 )             MI16( 1, imm16 )        R8( 2, b3 - 0x20 )      return;     // LD (mn),r
  610                  case 0x37:
  611                      OP( LD,12 )             MI16( 1, imm16 )        I8( 2, READ8(cpustate) )        return;     // LD (vw),n
  612                  case 0x3f:
  613                      OP( LDW,16 )            MI16( 1, imm16 )        I16( 2, READ16(cpustate) )      return;     // LDW (vw),mn
  614                  case 0x40:  case 0x41:  case 0x42:  /*case 0x43:*/  case 0x44:  case 0x45:  case 0x46:
  615                      OP16( LD,12 )           MI16( 1, imm16 )        R16( 2, b3 - 0x40 )     return;     // LD (mn),rr
  616  
  617                  case 0x68:                                                                              // ADD (vw),n
  618                  case 0x69:                                                                              // ADC (vw),n
  619                  case 0x6a:                                                                              // SUB (vw),n
  620                  case 0x6b:                                                                              // SBC (vw),n
  621                  case 0x6c:                                                                              // AND (vw),n
  622                  case 0x6d:                                                                              // XOR (vw),n
  623                  case 0x6e:                                                                              // OR  (vw),n
  624                      OP( ADD+b3-0x68,14 )    MI16( 1, imm16 )        I8( 2, READ8(cpustate) )        return;
  625                  case 0x6f:                                                                              // CP  (vw),n
  626                      OP( ADD+b3-0x68,12 )    MI16( 1, imm16 )        I8( 2, READ8(cpustate) )        return;
  627  
  628                  case 0xc0:  case 0xc1:  case 0xc2:  case 0xc3:  case 0xc4:  case 0xc5:  case 0xc6:  case 0xc7:
  629                  case 0xc8:  case 0xc9:  case 0xca:  case 0xcb:  case 0xcc:  case 0xcd:  case 0xce:  case 0xcf:
  630                      OPCC( JP,10,12 )        CC( 1, b3 - 0xc0 )      I16( 2, imm16 )         return;     // JP cc,mn
  631                  case 0xd0:  case 0xd1:  case 0xd2:  case 0xd3:  case 0xd4:  case 0xd5:  case 0xd6:  case 0xd7:
  632                  case 0xd8:  case 0xd9:  case 0xda:  case 0xdb:  case 0xdc:  case 0xdd:  case 0xde:  case 0xdf:
  633                      OPCC( CALL,10,18 )      CC( 1, b3 - 0xd0 )      I16( 2, imm16 )         return;     // CALL cc,mn
  634              }   break;
  635  
  636          case 0xef:
  637              b1 = READ8(cpustate);
  638              b2 = READ8(cpustate);
  639              switch ( b2 )   {
  640                  case 0x20:  case 0x21:  case 0x22:  case 0x23:  case 0x24:  case 0x25:  case 0x26:
  641                      OP( LD,8 )              MI16( 1, 0xFF00|b1 )    R8( 2, b2 - 0x20 )      return;     // LD ($FF00+n),r
  642                  case 0x40:  case 0x41:  case 0x42:  /*case 0x43:*/  case 0x44:  case 0x45:  case 0x46:
  643                      OP16( LD,10 )           MI16( 1, 0xFF00|b1 )    R16( 2, b2 - 0x40 )     return;     // LD ($FF00+n),rr
  644  
  645                  case 0x68:                                                                              // ADD ($FF00+w),n
  646                  case 0x69:                                                                              // ADC ($FF00+w),n
  647                  case 0x6a:                                                                              // SUB ($FF00+w),n
  648                  case 0x6b:                                                                              // SBC ($FF00+w),n
  649                  case 0x6c:                                                                              // AND ($FF00+w),n
  650                  case 0x6d:                                                                              // XOR ($FF00+w),n
  651                  case 0x6e:                                                                              // OR  ($FF00+w),n
  652                      OP( ADD+b2-0x68,12 )    MI16( 1, 0xFF00|b1 )    I8( 2, READ8(cpustate) )        return;
  653                  case 0x6f:                                                                              // CP  ($FF00+w),n
  654                      OP( ADD+b2-0x68,10 )    MI16( 1, 0xFF00|b1 )    I8( 2, READ8(cpustate) )        return;
  655              }   break;
  656  
  657          case 0xf0:  case 0xf1:  case 0xf2:
  658              b1 = READ8(cpustate);
  659              b2 = READ8(cpustate);
  660              switch ( b2 )   {
  661                  case 0x10:                                                                              // RLD (ix+d)
  662                  case 0x11:                                                                              // RRD (ix+d)
  663                      OP( RLD+b2-0x10,16 )    MR16D8( 1, IX + b0 - 0xf0, b1 )     NONE( 2 )   return;
  664  
  665                  case 0x12:                                                                              // MUL HL,(ix+d)
  666                  case 0x13:                                                                              // DIV HL,(ix+d)
  667                      OP( MUL+b2-0x12,22 )    R16( 1, HL )    MR16D8( 2, IX + b0 - 0xf0, b1 ) return;
  668  
  669                  case 0x14:  case 0x15:  case 0x16:
  670                      OP16( ADD,12 )  R16( 1, IX+b2-0x14 )    MR16D8( 2, IX + b0 - 0xf0, b1 ) return;     // ADD ix,(jx+d)
  671  
  672                  case 0x28:  case 0x29:  case 0x2a:  case 0x2b:  case 0x2c:  case 0x2d:  case 0x2e:
  673                      OP( LD,10 )     R8( 1, b2 - 0x28 )  MR16D8( 2, IX + b0 - 0xf0, b1 )     return;     // LD r,(ix+d)
  674                  case 0x48:  case 0x49:  case 0x4a:  /*case 0x4b:*/  case 0x4c:  case 0x4d:  case 0x4e:
  675                      OP16( LD,12 )   R16( 1, b2 - 0x48 ) MR16D8( 2, IX + b0 - 0xf0, b1 )     return;     // LD rr,(ix+d)
  676  
  677                  case 0x50:  case 0x51:  case 0x52:  /*case 0x53:*/  case 0x54:  case 0x55:  case 0x56:
  678                      OP( EX,18 )     MR16D8( 1, IX + b0 - 0xf0, b1 ) R16( 2, b2 - 0x50 )     return;     // EX (ix+d),rr
  679  
  680                  case 0x60:                                                                              // ADD A,(ix+d)
  681                  case 0x61:                                                                              // ADC A,(ix+d)
  682                  case 0x62:                                                                              // SUB A,(ix+d)
  683                  case 0x63:                                                                              // SBC A,(ix+d)
  684                  case 0x64:                                                                              // AND A,(ix+d)
  685                  case 0x65:                                                                              // XOR A,(ix+d)
  686                  case 0x66:                                                                              // OR  A,(ix+d)
  687                  case 0x67:                                                                              // CP  A,(ix+d)
  688                      OP( ADD+b2-0x60,10 )    R8( 1, A )  MR16D8( 2, IX + b0 - 0xf0, b1 )     return;
  689  
  690                  case 0x70:                                                                              // ADD HL,(ix+d)
  691                  case 0x71:                                                                              // ADC HL,(ix+d)
  692                  case 0x72:                                                                              // SUB HL,(ix+d)
  693                  case 0x73:                                                                              // SBC HL,(ix+d)
  694                  case 0x74:                                                                              // AND HL,(ix+d)
  695                  case 0x75:                                                                              // XOR HL,(ix+d)
  696                  case 0x76:                                                                              // OR  HL,(ix+d)
  697                  case 0x77:                                                                              // CP  HL,(ix+d)
  698                      OP16( ADD+b2-0x70,12 )  R16( 1, HL )    MR16D8( 2, IX + b0 - 0xf0, b1 ) return;
  699  
  700                  case 0x87:
  701                      OP( INC,12 )            MR16D8( 1, IX + b0 - 0xf0, b1 )     NONE( 2 )   return;     // INC (ix+d)
  702                  case 0x8f:
  703                      OP( DEC,12 )            MR16D8( 1, IX + b0 - 0xf0, b1 )     NONE( 2 )   return;     // DEC (ix+d)
  704  
  705                  case 0x97:
  706                      OP( INCW,16 )           MR16D8( 1, IX + b0 - 0xf0, b1 )     NONE( 2 )   return;     // INCW (ix+d)
  707                  case 0x9f:
  708                      OP( DECW,16 )           MR16D8( 1, IX + b0 - 0xf0, b1 )     NONE( 2 )   return;     // DECW (ix+d)
  709  
  710                  case 0xa0:                                                                              // RLC (ix+d)
  711                  case 0xa1:                                                                              // RRC (ix+d)
  712                  case 0xa2:                                                                              // RL  (ix+d)
  713                  case 0xa3:                                                                              // RR  (ix+d)
  714                  case 0xa4:                                                                              // SLA (ix+d)
  715                  case 0xa5:                                                                              // SRA (ix+d)
  716                  case 0xa6:                                                                              // SLL (ix+d)
  717                  case 0xa7:                                                                              // SRL (ix+d)
  718                      OP( RLC+b2-0xa0,12 )    MR16D8( 1, IX + b0 - 0xf0, b1 )     NONE( 2 )   return;
  719  
  720                  case 0x18:  case 0x19:  case 0x1a:  case 0x1b:  case 0x1c:  case 0x1d:  case 0x1e:  case 0x1f:
  721                      OP( TSET,16 )   BIT8( 1, b2 - 0x18 )    MR16D8( 2, IX + b0 - 0xf0, b1 ) return;     // TSET b,(ix+d)
  722                  case 0xa8:  case 0xa9:  case 0xaa:  case 0xab:  case 0xac:  case 0xad:  case 0xae:  case 0xaf:
  723                      OP( BIT,10 )    BIT8( 1, b2 - 0xa8 )    MR16D8( 2, IX + b0 - 0xf0, b1 ) return;     // BIT b,(ix+d)
  724                  case 0xb0:  case 0xb1:  case 0xb2:  case 0xb3:  case 0xb4:  case 0xb5:  case 0xb6:  case 0xb7:
  725                      OP( RES,14 )    BIT8( 1, b2 - 0xb0 )    MR16D8( 2, IX + b0 - 0xf0, b1 ) return;     // RES b,(ix+d)
  726                  case 0xb8:  case 0xb9:  case 0xba:  case 0xbb:  case 0xbc:  case 0xbd:  case 0xbe:  case 0xbf:
  727                      OP( SET,14 )    BIT8( 1, b2 - 0xb8 )    MR16D8( 2, IX + b0 - 0xf0, b1 ) return;     // SET b,(ix+d)
  728              }   break;
  729  
  730          case 0xf3:
  731              b1 = READ8(cpustate);
  732              switch ( b1 )   {
  733                  case 0x10:                                                                              // RLD (HL+A)
  734                  case 0x11:                                                                              // RRD (HL+A)
  735                      OP( RLD+b1-0x10,20 )    MR16R8( 1, HL, A )          NONE( 2 )           return;
  736  
  737                  case 0x12:                                                                              // MUL HL,(HL+A)
  738                  case 0x13:                                                                              // DIV HL,(HL+A)
  739                      OP( MUL+b1-0x12,26 )    R16( 1, HL )                MR16R8( 2, HL, A )  return;
  740  
  741                  case 0x14:  case 0x15:  case 0x16:
  742                      OP16( ADD,16 )          R16( 1, IX+b1-0x14 )        MR16R8( 2, HL, A )  return;     // ADD ix,(HL+A)
  743  
  744                  case 0x28:  case 0x29:  case 0x2a:  case 0x2b:  case 0x2c:  case 0x2d:  case 0x2e:
  745                      OP( LD,14 )             R8( 1, b1 - 0x28 )          MR16R8( 2, HL, A )  return;     // LD r,(HL+A)
  746                  case 0x48:  case 0x49:  case 0x4a:  /*case 0x4b:*/  case 0x4c:  case 0x4d:  case 0x4e:
  747                      OP16( LD,16 )           R16( 1, b1 - 0x48 )         MR16R8( 2, HL, A )  return;     // LD rr,(HL+A)
  748  
  749                  case 0x50:  case 0x51:  case 0x52:  /*case 0x53:*/  case 0x54:  case 0x55:  case 0x56:
  750                      OP( EX,22 )             MR16R8( 1, HL, A )          R16( 2, b1 - 0x50 ) return;     // EX (HL+A),rr
  751  
  752                  case 0x60:                                                                              // ADD A,(HL+A)
  753                  case 0x61:                                                                              // ADC A,(HL+A)
  754                  case 0x62:                                                                              // SUB A,(HL+A)
  755                  case 0x63:                                                                              // SBC A,(HL+A)
  756                  case 0x64:                                                                              // AND A,(HL+A)
  757                  case 0x65:                                                                              // XOR A,(HL+A)
  758                  case 0x66:                                                                              // OR  A,(HL+A)
  759                  case 0x67:                                                                              // CP  A,(HL+A)
  760                      OP( ADD+b1-0x60,14 )    R8( 1, A )                  MR16R8( 2, HL, A )  return;
  761  
  762                  case 0x70:                                                                              // ADD HL,(HL+A)
  763                  case 0x71:                                                                              // ADC HL,(HL+A)
  764                  case 0x72:                                                                              // SUB HL,(HL+A)
  765                  case 0x73:                                                                              // SBC HL,(HL+A)
  766                  case 0x74:                                                                              // AND HL,(HL+A)
  767                  case 0x75:                                                                              // XOR HL,(HL+A)
  768                  case 0x76:                                                                              // OR  HL,(HL+A)
  769                  case 0x77:                                                                              // CP  HL,(HL+A)
  770                      OP16( ADD+b1-0x70,16 )  R16( 1, HL )                MR16R8( 2, HL, A )  return;
  771  
  772                  case 0x87:
  773                      OP( INC,16 )            MR16R8( 1, HL, A )          NONE( 2 )           return;     // INC (HL+A)
  774                  case 0x8f:
  775                      OP( DEC,16 )            MR16R8( 1, HL, A )          NONE( 2 )           return;     // DEC (HL+A)
  776  
  777                  case 0x97:
  778                      OP( INCW,20 )           MR16R8( 1, HL, A )          NONE( 2 )           return;     // INCW (HL+A)
  779                  case 0x9f:
  780                      OP( DECW,20 )           MR16R8( 1, HL, A )          NONE( 2 )           return;     // DECW (HL+A)
  781  
  782                  case 0xa0:                                                                              // RLC (HL+A)
  783                  case 0xa1:                                                                              // RRC (HL+A)
  784                  case 0xa2:                                                                              // RL  (HL+A)
  785                  case 0xa3:                                                                              // RR  (HL+A)
  786                  case 0xa4:                                                                              // SLA (HL+A)
  787                  case 0xa5:                                                                              // SRA (HL+A)
  788                  case 0xa6:                                                                              // SLL (HL+A)
  789                  case 0xa7:                                                                              // SRL (HL+A)
  790                      OP( RLC+b1-0xa0,16 )    MR16R8( 1, HL, A )          NONE( 2 )           return;
  791  
  792                  case 0x18:  case 0x19:  case 0x1a:  case 0x1b:  case 0x1c:  case 0x1d:  case 0x1e:  case 0x1f:
  793                      OP( TSET,20 )           BIT8( 1, b1 - 0x18 )        MR16R8( 2, HL, A )  return;     // TSET b,(HL+A)
  794                  case 0xa8:  case 0xa9:  case 0xaa:  case 0xab:  case 0xac:  case 0xad:  case 0xae:  case 0xaf:
  795                      OP( BIT,14 )            BIT8( 1, b1 - 0xa8 )        MR16R8( 2, HL, A )  return;     // BIT b,(HL+A)
  796                  case 0xb0:  case 0xb1:  case 0xb2:  case 0xb3:  case 0xb4:  case 0xb5:  case 0xb6:  case 0xb7:
  797                      OP( RES,18 )            BIT8( 1, b1 - 0xb0 )        MR16R8( 2, HL, A )  return;     // RES b,(HL+A)
  798                  case 0xb8:  case 0xb9:  case 0xba:  case 0xbb:  case 0xbc:  case 0xbd:  case 0xbe:  case 0xbf:
  799                      OP( SET,18 )            BIT8( 1, b1 - 0xb8 )        MR16R8( 2, HL, A )  return;     // SET b,(HL+A)
  800              }   break;
  801  
  802          case 0xf4:  case 0xf5:  case 0xf6:
  803              b1 = READ8(cpustate);
  804              b2 = READ8(cpustate);
  805              switch ( b2 )   {
  806                  case 0x20:  case 0x21:  case 0x22:  case 0x23:  case 0x24:  case 0x25:  case 0x26:
  807                      OP( LD,10 )     MR16D8( 1, IX + b0 - 0xf4, b1 ) R8( 2, b2 - 0x20 )      return;     // LD (ix+d),r
  808                  case 0x37:
  809                      OP( LD,12 )     MR16D8( 1, IX + b0 - 0xf4, b1 ) I8( 2, READ8(cpustate) )        return;     // LD (ix+d),n
  810                  case 0x38:  case 0x39:  case 0x3a:  /*case 0x3b:*/  case 0x3c:  case 0x3d:  case 0x3e:
  811                      OP( LDA,10 )    R16( 1, b2 - 0x38 )     R16D8( 2, IX + b0 - 0xf4, b1 )  return;     // LDA rr,ix+d
  812                  case 0x3f:
  813                      OP( LDW,16 )    MR16D8( 1, IX + b0 - 0xf4, b1 ) I16( 2, READ16(cpustate) )      return;     // LDW (ix+d),mn
  814                  case 0x40:  case 0x41:  case 0x42:  /*case 0x43:*/  case 0x44:  case 0x45:  case 0x46:
  815                      OP16( LD,12 )   MR16D8( 1, IX + b0 - 0xf4, b1 ) R16( 2, b2 - 0x40 )     return;     // LD (ix+d),rr
  816  
  817                  case 0x68:                                                                              // ADD (ix+d),n
  818                  case 0x69:                                                                              // ADC (ix+d),n
  819                  case 0x6a:                                                                              // SUB (ix+d),n
  820                  case 0x6b:                                                                              // SBC (ix+d),n
  821                  case 0x6c:                                                                              // AND (ix+d),n
  822                  case 0x6d:                                                                              // XOR (ix+d),n
  823                  case 0x6e:                                                                              // OR  (ix+d),n
  824                      OP( ADD+b2-0x68,14) MR16D8( 1, IX + b0 - 0xf4, b1 ) I8( 2, READ8(cpustate) )    return;
  825                  case 0x6f:                                                                              // CP  (ix+d),n
  826                      OP( ADD+b2-0x68,12) MR16D8( 1, IX + b0 - 0xf4, b1 ) I8( 2, READ8(cpustate) )    return;
  827  
  828                  case 0xc0:  case 0xc1:  case 0xc2:  case 0xc3:  case 0xc4:  case 0xc5:  case 0xc6:  case 0xc7:
  829                  case 0xc8:  case 0xc9:  case 0xca:  case 0xcb:  case 0xcc:  case 0xcd:  case 0xce:  case 0xcf:
  830                      OPCC( JP,10,12 )    CC( 1, b2 - 0xc0 )  R16D8( 2, IX + b0 - 0xf4, b1 )  return;     // JP [cc,]ix+d
  831                  case 0xd0:  case 0xd1:  case 0xd2:  case 0xd3:  case 0xd4:  case 0xd5:  case 0xd6:  case 0xd7:
  832                  case 0xd8:  case 0xd9:  case 0xda:  case 0xdb:  case 0xdc:  case 0xdd:  case 0xde:  case 0xdf:
  833                      OPCC( CALL,10,18 )  CC( 1, b2 - 0xd0 )  R16D8( 2, IX + b0 - 0xf4, b1 )  return;     // CALL [cc,]ix+d
  834              }   break;
  835  
  836          case 0xf7:
  837              b1 = READ8(cpustate);
  838              switch ( b1 )   {
  839                  case 0x20:  case 0x21:  case 0x22:  case 0x23:  case 0x24:  case 0x25:  case 0x26:
  840                      OP( LD,14 )         MR16R8( 1, HL, A )      R8( 2, b1 - 0x20 )          return;     // LD (HL+A),r
  841                  case 0x37:
  842                      OP( LD,16 )         MR16R8( 1, HL, A )      I8( 2, READ8(cpustate) )            return;     // LD (HL+A),n
  843                  case 0x38:  case 0x39:  case 0x3a:  /*case 0x3b:*/  case 0x3c:  case 0x3d:  case 0x3e:
  844                      OP( LDA,14 )        R16( 1, b1 - 0x38 )     R16R8( 2, HL, A )           return;     // LDA rr,HL+A
  845                  case 0x3f:
  846                      OP( LDW,20 )        MR16R8( 1, HL, A )      I16( 2, READ16(cpustate) )          return;     // LDW (HL+A),mn
  847                  case 0x40:  case 0x41:  case 0x42:  /*case 0x43:*/  case 0x44:  case 0x45:  case 0x46:
  848                      OP16( LD,16 )       MR16R8( 1, HL, A )      R16( 2, b1 - 0x40 )         return;     // LD (HL+A),rr
  849  
  850                  case 0x68:                                                                              // ADD (HL+A),n
  851                  case 0x69:                                                                              // ADC (HL+A),n
  852                  case 0x6a:                                                                              // SUB (HL+A),n
  853                  case 0x6b:                                                                              // SBC (HL+A),n
  854                  case 0x6c:                                                                              // AND (HL+A),n
  855                  case 0x6d:                                                                              // XOR (HL+A),n
  856                  case 0x6e:                                                                              // OR  (HL+A),n
  857                      OP( ADD+b1-0x68,18) MR16R8( 1, HL, A )      I8( 2, READ8(cpustate) )            return;
  858                  case 0x6f:                                                                              // CP  (HL+A),n
  859                      OP( ADD+b1-0x68,16) MR16R8( 1, HL, A )      I8( 2, READ8(cpustate) )            return;
  860  
  861                  case 0xc0:  case 0xc1:  case 0xc2:  case 0xc3:  case 0xc4:  case 0xc5:  case 0xc6:  case 0xc7:
  862                  case 0xc8:  case 0xc9:  case 0xca:  case 0xcb:  case 0xcc:  case 0xcd:  case 0xce:  case 0xcf:
  863                      OPCC( JP,14,16 )    CC( 1, b1 - 0xc0 )      R16R8( 2, HL, A )           return;     // JP [cc,]HL+A
  864                  case 0xd0:  case 0xd1:  case 0xd2:  case 0xd3:  case 0xd4:  case 0xd5:  case 0xd6:  case 0xd7:
  865                  case 0xd8:  case 0xd9:  case 0xda:  case 0xdb:  case 0xdc:  case 0xdd:  case 0xde:  case 0xdf:
  866                      OPCC( CALL,14,22 )  CC( 1, b1 - 0xd0 )      R16R8( 2, HL, A )           return;     // CALL [cc,]HL+A
  867              }   break;
  868  
  869          case 0xf8:  case 0xf9:  case 0xfa:  case 0xfb:  case 0xfc:  case 0xfd:  case 0xfe:
  870              b1 = READ8(cpustate);
  871              switch ( b1 )   {
  872                  case 0x12:                                                                              // MUL HL,g
  873                  case 0x13:                                                                              // DIV HL,g
  874                      OP( MUL+b1-0x12,18) R16( 1, HL )            R8( 2, b0 - 0xf8 )          return;
  875  
  876                  case 0x14:  case 0x15:  case 0x16:
  877                      OP16( ADD,8 )       R16( 1, IX+b1-0x14 )    R16( 2, b0 - 0xf8 )         return;     // ADD ix,gg
  878  
  879                  case 0x30:  case 0x31:  case 0x32:  case 0x33:  case 0x34:  case 0x35:  case 0x36:
  880                      OP( LD,4 )          R8( 1, b1 - 0x30 )      R8( 2, b0 - 0xf8 )          return;     // LD r,g
  881                  case 0x38:  case 0x39:  case 0x3a:  /*case 0x3b:*/  case 0x3c:  case 0x3d:  case 0x3e:
  882                      OP16( LD,6 )        R16( 1, b1 - 0x38 )     R16( 2, b0 - 0xf8 )         return;     // LD rr,gg
  883  
  884                  case 0x58:                                                                              // LDI
  885                  case 0x59:                                                                              // LDIR
  886                  case 0x5a:                                                                              // LDD
  887                  case 0x5b:                                                                              // LDDR
  888                  case 0x5c:                                                                              // CPI
  889                  case 0x5d:                                                                              // CPIR
  890                  case 0x5e:                                                                              // CPD
  891                  case 0x5f:                                                                              // CPDR
  892                  if (b0 == 0xfe) {
  893                      OPCC( LDI+b1-0x58,14,18 )   NONE( 1 )       NONE( 2 )                   return;
  894                  }
  895  
  896                  case 0x60:                                                                              // ADD A,g
  897                  case 0x61:                                                                              // ADC A,g
  898                  case 0x62:                                                                              // SUB A,g
  899                  case 0x63:                                                                              // SBC A,g
  900                  case 0x64:                                                                              // AND A,g
  901                  case 0x65:                                                                              // XOR A,g
  902                  case 0x66:                                                                              // OR  A,g
  903                  case 0x67:                                                                              // CP  A,g
  904                      OP( ADD+b1-0x60,4 ) R8( 1, A )              R8( 2, b0 - 0xf8 )          return;
  905  
  906                  case 0x68:                                                                              // ADD g,n
  907                  case 0x69:                                                                              // ADC g,n
  908                  case 0x6a:                                                                              // SUB g,n
  909                  case 0x6b:                                                                              // SBC g,n
  910                  case 0x6c:                                                                              // AND g,n
  911                  case 0x6d:                                                                              // XOR g,n
  912                  case 0x6e:                                                                              // OR  g,n
  913                  case 0x6f:                                                                              // CP  g,n
  914                      OP( ADD+b1-0x68,6 ) R8( 1, b0 - 0xf8 )      I8( 2, READ8(cpustate) )            return;
  915  
  916                  case 0x70:                                                                              // ADD HL,gg
  917                  case 0x71:                                                                              // ADC HL,gg
  918                  case 0x72:                                                                              // SUB HL,gg
  919                  case 0x73:                                                                              // SBC HL,gg
  920                  case 0x74:                                                                              // AND HL,gg
  921                  case 0x75:                                                                              // XOR HL,gg
  922                  case 0x76:                                                                              // OR  HL,gg
  923                  case 0x77:                                                                              // CP  HL,gg
  924                      OP16( ADD+b1-0x70,8 )   R16( 1, HL )        R16( 2, b0 - 0xf8 )         return;
  925  
  926                  case 0xa0:                                                                              // RLC g
  927                  case 0xa1:                                                                              // RRC g
  928                  case 0xa2:                                                                              // RL  g
  929                  case 0xa3:                                                                              // RR  g
  930                  case 0xa4:                                                                              // SLA g
  931                  case 0xa5:                                                                              // SRA g
  932                  case 0xa6:                                                                              // SLL g
  933                  case 0xa7:                                                                              // SRL g
  934                      OP( RLC+b1-0xa0,4 ) R8( 1, b0 - 0xf8 )      NONE( 2 )                   return;
  935  
  936                  case 0x18:  case 0x19:  case 0x1a:  case 0x1b:  case 0x1c:  case 0x1d:  case 0x1e:  case 0x1f:
  937                      OP( TSET,8 )        BIT8( 1, b1 - 0x18 )    R8( 2, b0 - 0xf8 )          return;     // TSET b,g
  938                  case 0xa8:  case 0xa9:  case 0xaa:  case 0xab:  case 0xac:  case 0xad:  case 0xae:  case 0xaf:
  939                      OP( BIT,4 )         BIT8( 1, b1 - 0xa8 )    R8( 2, b0 - 0xf8 )          return;     // BIT b,g
  940                  case 0xb0:  case 0xb1:  case 0xb2:  case 0xb3:  case 0xb4:  case 0xb5:  case 0xb6:  case 0xb7:
  941                      OP( RES,4 )         BIT8( 1, b1 - 0xb0 )    R8( 2, b0 - 0xf8 )          return;     // RES b,g
  942                  case 0xb8:  case 0xb9:  case 0xba:  case 0xbb:  case 0xbc:  case 0xbd:  case 0xbe:  case 0xbf:
  943                      OP( SET,4 )         BIT8( 1, b1 - 0xb8 )    R8( 2, b0 - 0xf8 )          return;     // SET b,g
  944  
  945                  case 0xd0:  case 0xd1:  case 0xd2:  case 0xd3:  case 0xd4:  case 0xd5:  case 0xd6:  case 0xd7:
  946                  case 0xd8:  case 0xd9:  case 0xda:  case 0xdb:  case 0xdc:  case 0xdd:  case 0xde:  case 0xdf:
  947                  if (b0 == 0xfe) {
  948                      OPCC( RET,6,14 )    CC( 1, b1 - 0xd0 )      NONE( 2 )                   return;     // RET cc
  949                  }
  950              }   break;
  951  
  952          case 0xff:
  953              OP( SWI,20 )                NONE( 1 )               NONE( 2 )                   return;     // SWI
  954      }
  955  
  956      OP( UNKNOWN,2 )     NONE( 1 )       NONE( 2 )
  957  }
  958  
  959  static const char *const ir_names[] =   {
  960      "P0",       "P1",       "P01CR/IRFL",   "IRFH",     "P2",       "P2CR",     "P3",       "P3CR",
  961      "P4",       "P4CR",     "P5",           "SMMOD",    "P6",       "P7",       "P67CR",    "SMCR",
  962      "P8",       "P8CR",     "WDMOD",        "WDCR",     "TREG0",    "TREG1",    "TREG2",    "TREG3",
  963      "TCLK",     "TFFCR",    "TMOD",         "TRUN",     "CAP1L",    "CAP1H",    "CAP2L",    "CAL2H",
  964      "TREG4L",   "TREG4H",   "TREG5L",       "TREG5H",   "T4MOD",    "T4FFCR",   "INTEL",    "INTEH",
  965      "DMAEH",    "SCMOD",    "SCCR",         "SCBUF",    "BX",       "BY",       "ADREG",    "ADMOD"
  966  };
  967  
  968  static const char *internal_registers_names(UINT16 x)
  969  {
  970      int ir = x - T90_IOBASE;
  971      if ( ir >= 0 && ir < sizeof(ir_names)/sizeof(ir_names[0]) )
  972          return ir_names[ir];
  973      return NULL;
  974  }
  975  static int sprint_arg(char *buffer, UINT32 pc, const char *pre, const e_mode mode, const e_r r, const e_r rb)
  976  {
  977      const char *reg_name;
  978      switch ( mode )
  979      {
  980          case MODE_NONE:     return 0;
  981  
  982          case MODE_BIT8:     return  sprintf( buffer, "%s%d",            pre,    r                                   );
  983          case MODE_I8:       return  sprintf( buffer, "%s$%02X",         pre,    r                                   );
  984          case MODE_D8:       return  sprintf( buffer, "%s$%04X",         pre,    (pc+2+(r&0x7f)-(r&0x80))&0xffff     );
  985          case MODE_I16:      return  sprintf( buffer, "%s$%04X",         pre,    r                                   );
  986          case MODE_D16:      return  sprintf( buffer, "%s$%04X",         pre,    (pc+2+(r&0x7fff)-(r&0x8000))&0xffff );
  987          case MODE_MI16:
  988              reg_name = internal_registers_names(r);
  989              return  (reg_name) ?    sprintf( buffer, "%s(%s)",          pre,    reg_name                            ):
  990                                      sprintf( buffer, "%s($%04X)",       pre,    r                                   );
  991          case MODE_R8:       return  sprintf( buffer, "%s%s",            pre,    r8_names[r]                         );
  992          case MODE_R16:      return  sprintf( buffer, "%s%s",            pre,    r16_names[r]                        );
  993          case MODE_MR16:     return  sprintf( buffer, "%s(%s)",          pre,    r16_names[r]                        );
  994  
  995          case MODE_MR16R8:   return  sprintf( buffer, "%s(%s+%s)",       pre,    r16_names[r],   r8_names[rb]        );
  996          case MODE_MR16D8:   return  sprintf( buffer, "%s(%s%c$%02X)",   pre,    r16_names[r],   (rb&0x80)?'-':'+',  (rb&0x80)?((rb^0xff)+1):rb  );
  997  
  998          case MODE_CC:       return  sprintf( buffer, "%s%s",            pre,    cc_names[r]                         );
  999  
 1000          case MODE_R16R8:    return  sprintf( buffer, "%s%s+%s",         pre,    r16_names[r],   r8_names[rb]        );
 1001          case MODE_R16D8:    return  sprintf( buffer, "%s%s%c$%02X",     pre,    r16_names[r],   (rb&0x80)?'-':'+',  (rb&0x80)?((rb^0xff)+1):rb  );
 1002  
 1003          default:
 1004              fatalerror("%04x: unimplemented addr mode = %d\n",pc,mode);
 1005      }
 1006  
 1007      return 0;
 1008  }
 1009  
 1010  CPU_DISASSEMBLE( t90 )
 1011  {
 1012      t90_Regs *cpustate = get_safe_token(device);
 1013      int len;
 1014  
 1015      cpustate->addr = pc;
 1016  
 1017      decode(cpustate);
 1018      cpustate->op &= ~OP_16;
 1019  
 1020      buffer  +=  sprintf     ( buffer,           "%-5s",             op_names[ cpustate->op ] ); // strlen("callr") == 5
 1021      len     =   sprint_arg  ( buffer, pc,       " ",                cpustate->mode1, cpustate->r1, cpustate->r1b );
 1022      buffer  +=  len;
 1023      buffer  +=  sprint_arg  ( buffer, pc,       (len>1)?",":"",     cpustate->mode2, cpustate->r2, cpustate->r2b );
 1024  
 1025      return (cpustate->addr - pc) | DASMFLAG_SUPPORTED;
 1026  }
 1027  
 1028  
 1029  INLINE UINT16 r8( t90_Regs *cpustate, const e_r r )
 1030  {
 1031      switch( r )
 1032      {
 1033          case A: return cpustate->af.b.h;
 1034          case B: return cpustate->bc.b.h;
 1035          case C: return cpustate->bc.b.l;
 1036          case D: return cpustate->de.b.h;
 1037          case E: return cpustate->de.b.l;
 1038          case H: return cpustate->hl.b.h;
 1039          case L: return cpustate->hl.b.l;
 1040  
 1041          default:
 1042              fatalerror("%04x: unimplemented r8 register index = %d\n",cpustate->pc.w.l,r);
 1043      }
 1044  }
 1045  
 1046  INLINE void w8( t90_Regs *cpustate, const e_r r, UINT16 value )
 1047  {
 1048      switch( r )
 1049      {
 1050          case A: cpustate->af.b.h = value;   return;
 1051          case B: cpustate->bc.b.h = value;   return;
 1052          case C: cpustate->bc.b.l = value;   return;
 1053          case D: cpustate->de.b.h = value;   return;
 1054          case E: cpustate->de.b.l = value;   return;
 1055          case H: cpustate->hl.b.h = value;   return;
 1056          case L: cpustate->hl.b.l = value;   return;
 1057  
 1058          default:
 1059              fatalerror("%04x: unimplemented w8 register index = %d\n",cpustate->pc.w.l,r);
 1060      }
 1061  }
 1062  
 1063  INLINE UINT16 r16( t90_Regs *cpustate, const e_r r )
 1064  {
 1065      switch( r )
 1066      {
 1067          case BC:    return cpustate->bc.w.l;
 1068          case DE:    return cpustate->de.w.l;
 1069          case HL:    return cpustate->hl.w.l;
 1070          case IX:    return cpustate->ix.w.l;
 1071          case IY:    return cpustate->iy.w.l;
 1072          case SP:    return cpustate->sp.w.l;
 1073          case AF:    return cpustate->af.w.l;
 1074  //      case AF2:   return cpustate->af2.w.l;
 1075  // one interrupt flip-flop? Needed by e.g. mjifb
 1076          case AF2:   return (cpustate->af2.w.l & (~IF)) | (cpustate->af.w.l & IF);
 1077          case PC:    return cpustate->pc.w.l;
 1078  
 1079          default:
 1080              fatalerror("%04x: unimplemented r16 register index = %d\n",cpustate->pc.w.l,r);
 1081      }
 1082  }
 1083  
 1084  INLINE void w16( t90_Regs *cpustate, const e_r r, UINT16 value )
 1085  {
 1086      switch( r )
 1087      {
 1088          case BC:    cpustate->bc.w.l  = value;  return;
 1089          case DE:    cpustate->de.w.l  = value;  return;
 1090          case HL:    cpustate->hl.w.l  = value;  return;
 1091          case IX:    cpustate->ix.w.l  = value;  return;
 1092          case IY:    cpustate->iy.w.l  = value;  return;
 1093          case SP:    cpustate->sp.w.l  = value;  return;
 1094          case AF:    cpustate->af.w.l  = value;  return;
 1095          case AF2:   cpustate->af2.w.l = value;  return;
 1096          case PC:    cpustate->pc.d = value; return;
 1097  
 1098          default:
 1099              fatalerror("%04x: unimplemented w16 register index = %d\n",cpustate->pc.w.l,r);
 1100      }
 1101  }
 1102  
 1103  
 1104  #define READ_FN( N ) \
 1105  INLINE UINT8 Read##N##_8(t90_Regs *cpustate)    { \
 1106      switch ( cpustate->mode##N )    { \
 1107          case MODE_CC: \
 1108          case MODE_BIT8: \
 1109          case MODE_I8:       return (UINT8)cpustate->r##N; \
 1110          case MODE_D8:       return (UINT8)cpustate->r##N; \
 1111          case MODE_R8:       return (UINT8)r8(cpustate, cpustate->r##N); \
 1112          case MODE_MI16:     return RM8(cpustate, cpustate->r##N); \
 1113          case MODE_MR16R8:   return RM8(cpustate, (UINT16)(r16(cpustate, cpustate->r##N) + (INT8)r8(cpustate, cpustate->r##N##b))); \
 1114          case MODE_MR16: \
 1115              switch( cpustate->r##N ) { \
 1116                  case IX:    return RX8(cpustate, cpustate->ix.w.l,cpustate->ixbase); \
 1117                  case IY:    return RX8(cpustate, cpustate->iy.w.l,cpustate->iybase); \
 1118              } \
 1119              return RM8(cpustate, r16(cpustate, cpustate->r##N)); \
 1120          case MODE_MR16D8: \
 1121              switch( cpustate->r##N ) { \
 1122                  case IX:    return RX8(cpustate, (UINT16)(cpustate->ix.w.l + (INT8)cpustate->r##N##b),cpustate->ixbase); \
 1123                  case IY:    return RX8(cpustate, (UINT16)(cpustate->iy.w.l + (INT8)cpustate->r##N##b),cpustate->iybase); \
 1124              } \
 1125              return RM8(cpustate, (UINT16)(r16(cpustate, cpustate->r##N) + (INT8)cpustate->r##N##b)); \
 1126          default: \
 1127              fatalerror("%04x: unimplemented Read%d_8 mode = %d\n",cpustate->pc.w.l,N,cpustate->mode##N); \
 1128      } \
 1129      return 0; \
 1130  } \
 1131  INLINE UINT16 Read##N##_16(t90_Regs *cpustate)  { \
 1132      switch ( cpustate->mode##N )    { \
 1133          case MODE_I16:      return cpustate->r##N; \
 1134          case MODE_D16:      return cpustate->r##N - 1; \
 1135          case MODE_R16:      return r16(cpustate, cpustate->r##N); \
 1136          case MODE_R16D8:    return r16(cpustate, cpustate->r##N) + (INT8)cpustate->r##N##b; \
 1137          case MODE_R16R8:    return r16(cpustate, cpustate->r##N) + (INT8)r8(cpustate, cpustate->r##N##b); \
 1138          case MODE_MI16:     return RM16(cpustate, cpustate->r##N); \
 1139          case MODE_MR16R8:   return RM16(cpustate,(UINT16)(r16(cpustate, cpustate->r##N) + (INT8)r8(cpustate, cpustate->r##N##b))); \
 1140          case MODE_MR16: \
 1141              switch( cpustate->r##N ) { \
 1142                  case IX:    return RX16(cpustate, cpustate->ix.w.l,cpustate->ixbase); \
 1143                  case IY:    return RX16(cpustate, cpustate->iy.w.l,cpustate->iybase); \
 1144              } \
 1145              return RM16(cpustate,r16(cpustate, cpustate->r##N)); \
 1146          case MODE_MR16D8: \
 1147              switch( cpustate->r##N ) { \
 1148                  case IX:    return RX16(cpustate, (UINT16)(cpustate->ix.w.l + (INT8)cpustate->r##N##b),cpustate->ixbase); \
 1149                  case IY:    return RX16(cpustate, (UINT16)(cpustate->iy.w.l + (INT8)cpustate->r##N##b),cpustate->iybase); \
 1150              } \
 1151              return RM16(cpustate, (UINT16)(r16(cpustate, cpustate->r##N) + (INT8)cpustate->r##N##b)); \
 1152          default: \
 1153              fatalerror("%04x: unimplemented Read%d_16 modes = %d\n",cpustate->pc.w.l,N,cpustate->mode##N); \
 1154      } \
 1155      return 0; \
 1156  }
 1157  
 1158  
 1159  
 1160  #define WRITE_FN( N ) \
 1161  INLINE void Write##N##_8( t90_Regs *cpustate, UINT8 value ) { \
 1162      switch ( cpustate->mode##N )    { \
 1163          case MODE_R8:       w8(cpustate, cpustate->r##N,value);     return; \
 1164          case MODE_MI16:     WM8(cpustate, cpustate->r##N, value);   return; \
 1165          case MODE_MR16R8:   WM8(cpustate, (UINT16)(r16(cpustate, cpustate->r##N) + (INT8)r8(cpustate, cpustate->r##N##b)), value);  return; \
 1166          case MODE_MR16: \
 1167              switch( cpustate->r##N ) { \
 1168                  case IX:    WX8(cpustate, cpustate->ix.w.l,value,cpustate->ixbase); return; \
 1169                  case IY:    WX8(cpustate, cpustate->iy.w.l,value,cpustate->iybase); return; \
 1170              } \
 1171              WM8(cpustate, r16(cpustate, cpustate->r##N), value);    return; \
 1172          case MODE_MR16D8: \
 1173              switch( cpustate->r##N ) { \
 1174                  case IX:    WX8(cpustate, (UINT16)(cpustate->ix.w.l + (INT8)cpustate->r##N##b),value,cpustate->ixbase); return; \
 1175                  case IY:    WX8(cpustate, (UINT16)(cpustate->iy.w.l + (INT8)cpustate->r##N##b),value,cpustate->iybase); return; \
 1176              } \
 1177              WM8(cpustate, (UINT16)(r16(cpustate, cpustate->r##N) + (INT8)cpustate->r##N##b), value);    return; \
 1178          default: \
 1179              fatalerror("%04x: unimplemented Write%d_8 mode = %d\n",cpustate->pc.w.l,N,cpustate->mode##N); \
 1180      } \
 1181  } \
 1182  INLINE void Write##N##_16( t90_Regs *cpustate, UINT16 value ) \
 1183  { \
 1184      switch ( cpustate->mode##N )    { \
 1185          case MODE_R16:      w16(cpustate, cpustate->r##N,value);    return; \
 1186          case MODE_MI16:     WM16(cpustate, cpustate->r##N, value);  return; \
 1187          case MODE_MR16R8:   WM16(cpustate, (UINT16)(r16(cpustate, cpustate->r##N) + (INT8)r8(cpustate, cpustate->r##N##b)), value); return; \
 1188          case MODE_MR16: \
 1189              switch( cpustate->r##N ) { \
 1190                  case IX:    WX16(cpustate, cpustate->ix.w.l,value,cpustate->ixbase);    return; \
 1191                  case IY:    WX16(cpustate, cpustate->iy.w.l,value,cpustate->iybase);    return; \
 1192              } \
 1193              WM16(cpustate, r16(cpustate, cpustate->r##N), value);   return; \
 1194          case MODE_MR16D8: \
 1195              switch( cpustate->r##N ) { \
 1196                  case IX:    WX16(cpustate, (UINT16)(cpustate->ix.w.l + (INT8)cpustate->r##N##b),value,cpustate->ixbase);    return; \
 1197                  case IY:    WX16(cpustate, (UINT16)(cpustate->iy.w.l + (INT8)cpustate->r##N##b),value,cpustate->iybase);    return; \
 1198              } \
 1199              WM16(cpustate, (UINT16)(r16(cpustate, cpustate->r##N) + (INT8)cpustate->r##N##b), value);   return; \
 1200          default: \
 1201              fatalerror("%04x: unimplemented Write%d_16 mode = %d\n",cpustate->pc.w.l,N,cpustate->mode##N); \
 1202      } \
 1203  }
 1204  
 1205  READ_FN(1)
 1206  READ_FN(2)
 1207  WRITE_FN(1)
 1208  WRITE_FN(2)
 1209  
 1210  INLINE int Test( t90_Regs *cpustate, UINT8 cond )
 1211  {
 1212      int s,v;
 1213      switch ( cond )
 1214      {
 1215          case FLS:   return 0;
 1216          case LT:    s = F & SF; v = F & VF; return (s && !v) || (!s && v);
 1217          case LE:    s = F & SF; v = F & VF; return (F & ZF) || (s && !v) || (!s && v);
 1218          case ULE:   return (F & CF) || (F & ZF);
 1219          case OV:    return F & VF;
 1220          case MI:    return F & SF;
 1221          case Z:     return F & ZF;
 1222          case CR:    return F & CF;
 1223          case T:     return 1;
 1224          case GE:    s = F & SF; v = F & VF; return (s && v) || (!s && !v);
 1225          case GT:    s = F & SF; v = F & VF; return !((F & ZF) || (s && !v) || (!s && v));
 1226          case UGT:   return !(F & CF) && !(F & ZF);
 1227          case NOV:   return !(F & VF);
 1228          case PL:    return !(F & SF);
 1229          case NZ:    return !(F & ZF);
 1230          case NC:    return !(F & CF);
 1231          default:
 1232              fatalerror("%04x: unimplemented condition = %d\n",cpustate->pc.w.l,cond);
 1233      }
 1234      return 0;
 1235  }
 1236  
 1237  INLINE void Push( t90_Regs *cpustate, e_r rr )
 1238  {
 1239      cpustate->sp.w.l -= 2;
 1240      WM16( cpustate, cpustate->sp.w.l, r16(cpustate, rr) );
 1241  }
 1242  INLINE void Pop( t90_Regs *cpustate, e_r rr )
 1243  {
 1244      w16( cpustate, rr, RM16( cpustate, cpustate->sp.w.l ) );
 1245      cpustate->sp.w.l += 2;
 1246  }
 1247  
 1248  /*************************************************************************************************************
 1249  
 1250  Interrupts
 1251  
 1252  ----------------------------------------------------------------------------------------------------------------
 1253  Priority    Type            Interrupt Source            Vector/8    Vector  Address         uDMA Address
 1254  ----------------------------------------------------------------------------------------------------------------
 1255  1           Non Maskable    SWI                         -           10      0010            -
 1256  2           ""              NMI                         -           18      0018            -
 1257  3           ""              INTWD   Watch Dog           -           20      0020            -
 1258  4           Maskable        INT0    External 0          05          28      0028            FF28
 1259  5           ""              INTT0   Timer 0             06          30      0030            FF30
 1260  6           ""              INTT1   Timer 1             07          38      0038            FF38
 1261  7           ""              INTAD   A/D                 08          40      0040            FF48
 1262  ""          ""              INTT2   Timer 2             ""          ""      ""              ""
 1263  8           ""              INTT3   Timer 3             09          48      0048            FF48
 1264  9           ""              INTT4   Timer 4             0A          50      0050            FF50
 1265  10          ""              INT1    External 1          0B          58      0058            FF58
 1266  11          ""              INTT5   Timer 5             0C          60      0060            FF60
 1267  12          ""              INT2    External 2          0D          68      0068            FF68
 1268  13          ""              INTRX   End Serial Receive  0E          70      0070            FF70
 1269  14          ""              INTTX   End Serial Transmit 0F          78      0078            FF78
 1270  
 1271  ----------------------------------------------------------------------------------------------------------------
 1272  Interrupt   Terminal    Mode            How To Set
 1273  ----------------------------------------------------------------------------------------------------------------
 1274  NMI         -           Falling Edge    -
 1275  INT0        P80         Level           P8CR<EDGE> = 0
 1276                          Rising Edge     P8CR<EDGE> = 1
 1277  INT1        P81         Rising Edge     T4MOD<CAPM1,0> = 0,0 or 0,1 or 1,1
 1278                          Falling Edge    T4MOD<CAPM1,0> = 1,0
 1279  INT2        P82         Rising Edge     -
 1280  
 1281  *************************************************************************************************************/
 1282  
 1283  enum e_irq {    INTSWI = 0, INTNMI, INTWD,  INT0,   INTT0,  INTT1,  INTT2,  INTT3,  INTT4,  INT1,   INTT5,  INT2,   INTRX,  INTTX,  INTMAX  };
 1284  DECLARE_ENUM_OPERATORS(e_irq)
 1285  
 1286  INLINE void leave_halt(t90_Regs *cpustate)
 1287  {
 1288      if( cpustate->halt )
 1289      {
 1290          cpustate->halt = 0;
 1291          cpustate->pc.w.l++;
 1292      }
 1293  }
 1294  
 1295  static void take_interrupt(t90_Regs *cpustate, e_irq irq)
 1296  {
 1297      cpustate->irq_state &= ~(1 << irq);
 1298  
 1299      leave_halt(cpustate);
 1300  
 1301      Push( cpustate, PC );
 1302      Push( cpustate, AF );
 1303  
 1304      F &= ~IF;
 1305  
 1306      cpustate->pc.w.l = 0x10 + irq * 8;
 1307  
 1308      cpustate->extra_cycles += 20*2;
 1309  }
 1310  
 1311  static void check_interrupts(t90_Regs *cpustate)
 1312  {
 1313      e_irq irq;
 1314  
 1315      if (!(F & IF))
 1316          return;
 1317  
 1318      for (irq = INT0; irq < INTMAX; irq++)
 1319      {
 1320          if ( cpustate->irq_state & cpustate->irq_mask & (1 << irq) )
 1321          {
 1322              take_interrupt( cpustate, irq );
 1323              return;
 1324          }
 1325      }
 1326  }
 1327  
 1328  static void set_irq_line(t90_Regs *cpustate, int irq, int state)
 1329  {
 1330      if ( ((cpustate->irq_state >> irq)&1) == state ) return;
 1331  
 1332      if (state)
 1333      {
 1334          cpustate->irq_state |= 1 << irq;
 1335          check_interrupts(cpustate);
 1336      }
 1337      else
 1338      {
 1339          cpustate->irq_state &= ~(1 << irq);
 1340      }
 1341  }
 1342  
 1343  INLINE void Cyc(t90_Regs *cpustate) {   cpustate->icount -= cpustate->cyc_t;    }
 1344  INLINE void Cyc_f(t90_Regs *cpustate)   {   cpustate->icount -= cpustate->cyc_f;    }
 1345  
 1346  static CPU_EXECUTE( t90 )
 1347  {
 1348      t90_Regs *cpustate = get_safe_token(device);
 1349      UINT8    a8,b8;
 1350      UINT16   a16,b16;
 1351      unsigned a32;
 1352      PAIR tmp;
 1353  
 1354      cpustate->icount -= cpustate->extra_cycles;
 1355      cpustate->extra_cycles = 0;
 1356  
 1357      do
 1358      {
 1359          cpustate->prvpc.d = cpustate->pc.d;
 1360          debugger_instruction_hook(device, cpustate->pc.d);
 1361  
 1362          check_interrupts(cpustate);
 1363  
 1364          cpustate->addr = cpustate->pc.d;
 1365          decode(cpustate);
 1366          cpustate->pc.d = cpustate->addr;
 1367  
 1368          switch ( cpustate->op )
 1369          {
 1370              case NOP:
 1371                  Cyc(cpustate);
 1372                  break;
 1373  
 1374              case EX:
 1375                  a16 = Read1_16(cpustate);
 1376                  Write1_16( cpustate, Read2_16(cpustate) );
 1377                  Write2_16( cpustate, a16 );
 1378                  Cyc(cpustate);
 1379                  break;
 1380              case EXX:
 1381                  tmp = cpustate->bc; cpustate->bc = cpustate->bc2;   cpustate->bc2 = tmp;
 1382                  tmp = cpustate->de; cpustate->de = cpustate->de2;   cpustate->de2 = tmp;
 1383                  tmp = cpustate->hl; cpustate->hl = cpustate->hl2;   cpustate->hl2 = tmp;
 1384                  Cyc(cpustate);
 1385                  break;
 1386  
 1387              case LD:
 1388                  Write1_8( cpustate, Read2_8(cpustate) );
 1389                  Cyc(cpustate);
 1390                  break;
 1391              case LDW:
 1392              case LD | OP_16:
 1393                  Write1_16( cpustate, Read2_16(cpustate) );
 1394                  Cyc(cpustate);
 1395                  break;
 1396  
 1397  //          case LDA:
 1398  //              Cyc(cpustate);
 1399  //              break;
 1400  
 1401              case LDI:
 1402  #define _LDI                                            \
 1403                  WM8( cpustate, cpustate->de.w.l, RM8(cpustate, cpustate->hl.w.l) );     \
 1404                  cpustate->de.w.l++;                         \
 1405                  cpustate->hl.w.l++;                         \
 1406                  cpustate->bc.w.l--;                         \
 1407                  F &= SF | ZF | IF | XCF | CF;           \
 1408                  if ( cpustate->bc.w.l ) F |= VF;
 1409  
 1410                  _LDI
 1411                  Cyc(cpustate);
 1412                  break;
 1413              case LDIR:
 1414                  _LDI
 1415                  if ( cpustate->bc.w.l )
 1416                  {
 1417                      cpustate->pc.w.l -= 2;
 1418                      Cyc(cpustate);
 1419                  }
 1420                  else    Cyc_f(cpustate);
 1421                  break;
 1422  
 1423              case LDD:
 1424  #define _LDD                                            \
 1425                  WM8( cpustate, cpustate->de.w.l, RM8(cpustate, cpustate->hl.w.l) );     \
 1426                  cpustate->de.w.l--;                         \
 1427                  cpustate->hl.w.l--;                         \
 1428                  cpustate->bc.w.l--;                         \
 1429                  F &= SF | ZF | IF | XCF | CF;           \
 1430                  if ( cpustate->bc.w.l ) F |= VF;
 1431  
 1432                  _LDD
 1433                  Cyc(cpustate);
 1434                  break;
 1435              case LDDR:
 1436                  _LDD
 1437                  if ( cpustate->bc.w.l )
 1438                  {
 1439                      cpustate->pc.w.l -= 2;
 1440                      Cyc(cpustate);
 1441                  }
 1442                  else    Cyc_f(cpustate);
 1443                  break;
 1444  
 1445  
 1446  //          case CPD:
 1447  //              Cyc(cpustate);
 1448  //              break;
 1449  //          case CPDR:
 1450  //              Cyc(cpustate);
 1451  //              break;
 1452              case CPI:
 1453                  a8 = RM8(cpustate, cpustate->hl.w.l);
 1454                  b8 = cpustate->af.b.h - a8;
 1455                  cpustate->hl.w.l++;
 1456                  cpustate->bc.w.l--;
 1457                  F = (F & (IF | CF)) | SZ[b8] | ((cpustate->af.b.h^a8^b8)&HF) | NF;
 1458                  if ( cpustate->bc.w.l ) F |= VF;
 1459                  Cyc(cpustate);
 1460                  break;
 1461              case CPIR:
 1462                  a8 = RM8(cpustate, cpustate->hl.w.l);
 1463                  b8 = cpustate->af.b.h - a8;
 1464                  cpustate->hl.w.l++;
 1465                  cpustate->bc.w.l--;
 1466                  F = (F & (IF | CF)) | SZ[b8] | ((cpustate->af.b.h^a8^b8)&HF) | NF;
 1467                  if ( cpustate->bc.w.l )
 1468                  {
 1469                      F |= VF;
 1470                      cpustate->pc.w.l -= 2;
 1471                      Cyc(cpustate);
 1472                  }
 1473                  else    Cyc_f(cpustate);
 1474                  break;
 1475  
 1476              case PUSH:
 1477                  Push( cpustate, cpustate->r1 );
 1478                  Cyc(cpustate);
 1479                  break;
 1480              case POP:
 1481                  Pop( cpustate, cpustate->r1 );
 1482                  Cyc(cpustate);
 1483                  break;
 1484  
 1485              case JP:
 1486                  if ( Test( cpustate, Read1_8(cpustate) ) )
 1487                  {
 1488                      cpustate->pc.w.l = Read2_16(cpustate);
 1489                      Cyc(cpustate);
 1490                  }
 1491                  else    Cyc_f(cpustate);
 1492                  break;
 1493              case JR:
 1494                  if ( Test( cpustate, Read1_8(cpustate) ) )
 1495                  {
 1496                      cpustate->pc.w.l += /*2 +*/ (INT8)Read2_8(cpustate);
 1497                      Cyc(cpustate);
 1498                  }
 1499                  else    Cyc_f(cpustate);
 1500                  break;
 1501              case JR | OP_16:
 1502                  if ( Test( cpustate, Read1_8(cpustate) ) )
 1503                  {
 1504                      cpustate->pc.w.l += /*2 +*/ Read2_16(cpustate);
 1505                      Cyc(cpustate);
 1506                  }
 1507                  else    Cyc_f(cpustate);
 1508                  break;
 1509  
 1510  
 1511              case CALL:
 1512                  if ( Test( cpustate, Read1_8(cpustate) ) )
 1513                  {
 1514                      Push( cpustate, PC );
 1515                      cpustate->pc.w.l = Read2_16(cpustate);
 1516                      Cyc(cpustate);
 1517                  }
 1518                  else    Cyc_f(cpustate);
 1519                  break;
 1520              case CALLR:
 1521                  Push( cpustate, PC );
 1522                  cpustate->pc.w.l += /*2 +*/ Read1_16(cpustate);
 1523                  Cyc(cpustate);
 1524                  break;
 1525  
 1526              case RET:
 1527                  if ( Test( cpustate, Read1_8(cpustate) ) )
 1528                  {
 1529                      Pop( cpustate, PC );
 1530                      Cyc(cpustate);
 1531                  }
 1532                  else    Cyc_f(cpustate);
 1533                  break;
 1534              case RETI:
 1535                  Pop( cpustate, AF );
 1536                  Pop( cpustate, PC );
 1537                  Cyc(cpustate);
 1538                  break;
 1539  
 1540  //          case HALT:
 1541  //              Cyc(cpustate);
 1542  //              break;
 1543              case DI:
 1544                  cpustate->after_EI = 0;
 1545                  F &= ~IF;
 1546                  Cyc(cpustate);
 1547                  break;
 1548              case EI:
 1549                  cpustate->after_EI = !(F & IF);
 1550                  Cyc(cpustate);
 1551                  break;
 1552  
 1553              case SWI:
 1554                  Cyc(cpustate);
 1555                  take_interrupt( cpustate, INTSWI );
 1556                  break;
 1557  
 1558              case DAA:
 1559              {
 1560                  UINT8 cf, nf, hf, lo, hi, diff;
 1561                  cf = F & CF;
 1562                  nf = F & NF;
 1563                  hf = F & HF;
 1564                  lo = cpustate->af.b.h & 15;
 1565                  hi = cpustate->af.b.h / 16;
 1566  
 1567                  if (cf)
 1568                  {
 1569                      diff = (lo <= 9 && !hf) ? 0x60 : 0x66;
 1570                  }
 1571                  else
 1572                  {
 1573                      if (lo >= 10)
 1574                      {
 1575                          diff = hi <= 8 ? 0x06 : 0x66;
 1576                      }
 1577                      else
 1578                      {
 1579                          if (hi >= 10)
 1580                          {
 1581                              diff = hf ? 0x66 : 0x60;
 1582                          }
 1583                          else
 1584                          {
 1585                              diff = hf ? 0x06 : 0x00;
 1586                          }
 1587                      }
 1588                  }
 1589                  if (nf) cpustate->af.b.h -= diff;
 1590                  else cpustate->af.b.h += diff;
 1591  
 1592                  F = SZP[A] | (F & (IF | NF));
 1593                  if (cf || (lo <= 9 ? hi >= 10 : hi >= 9)) F |= XCF | CF;
 1594                  if (nf ? hf && lo <= 5 : lo >= 10)  F |= HF;
 1595              }
 1596                  Cyc(cpustate);
 1597                  break;
 1598  
 1599  
 1600              case CPL:
 1601                  cpustate->af.b.h ^= 0xff;
 1602                  F |= HF | NF;
 1603                  Cyc(cpustate);
 1604                  break;
 1605              case NEG:
 1606                  a8 = 0;
 1607                  b8 = cpustate->af.b.h;
 1608                  a32 = a8 - b8;
 1609                  F = (F & IF) | SZ[(UINT8)a32] | NF;
 1610                  if (a32 & 0x100)            F |= CF | XCF;  //X?
 1611                  if ((a8 ^ a32 ^ b8) & 0x10) F |= HF;
 1612                  if ((b8 ^ a8) & (a8 ^ a32) & 0x80)  F |= VF;
 1613                  cpustate->af.b.h = a32;
 1614                  Cyc(cpustate);
 1615                  break;
 1616  
 1617              case LDAR:
 1618                  cpustate->hl.w.l = cpustate->pc.w.l + /*2 +*/ Read2_16(cpustate);
 1619                  Cyc(cpustate);
 1620                  break;
 1621  
 1622              case RCF:
 1623                  F &= SF | ZF | IF | VF;
 1624                  Cyc(cpustate);
 1625                  break;
 1626              case SCF:
 1627                  F = (F & (SF | ZF | IF | VF)) | XCF | CF;
 1628                  Cyc(cpustate);
 1629                  break;
 1630              case CCF:
 1631                  F = (F & (SF | ZF | IF | VF)) | ((F & CF)?HF:(XCF | CF));
 1632                  Cyc(cpustate);
 1633                  break;
 1634  
 1635  //          case TSET:
 1636  //              Cyc(cpustate);
 1637  //              break;
 1638              case BIT:
 1639                  F = (F & (IF | CF)) | HF | SZ_BIT[ Read2_8(cpustate) & (1 << Read1_8(cpustate)) ];
 1640                  Cyc(cpustate);
 1641                  break;
 1642              case SET:
 1643                  Write2_8( cpustate, Read2_8(cpustate) | (1 << Read1_8(cpustate)) );
 1644                  Cyc(cpustate);
 1645                  break;
 1646              case RES:
 1647                  Write2_8( cpustate, Read2_8(cpustate) & (~(1 << Read1_8(cpustate))) );
 1648                  Cyc(cpustate);
 1649                  break;
 1650  
 1651              case INC:
 1652                  a8 = Read1_8(cpustate) + 1;
 1653                  Write1_8( cpustate, a8 );
 1654                  F = (F & (IF | CF)) | SZHV_inc[a8];
 1655                  if (a8 == 0)    F |= XCF;
 1656                  Cyc(cpustate);
 1657                  break;
 1658              case INCX:
 1659                  if ( F & XCF )
 1660                  {
 1661                      a8 = Read1_8(cpustate) + 1;
 1662                      Write1_8( cpustate, a8 );
 1663                      F = (F & (IF | CF)) | SZHV_inc[a8];
 1664                      if (a8 == 0)    F |= XCF;
 1665                      Cyc(cpustate);
 1666                  }
 1667                  else    Cyc_f(cpustate);
 1668                  break;
 1669              case INC | OP_16:
 1670                  a16 = Read1_16(cpustate) + 1;
 1671                  Write1_16( cpustate, a16 );
 1672                  if (a16 == 0)   F |=  XCF;
 1673                  else            F &= ~XCF;
 1674                  Cyc(cpustate);
 1675                  break;
 1676              case INCW:
 1677                  a16 = Read1_16(cpustate);
 1678                  a32 = a16 + 1;
 1679                  Write1_16( cpustate, a32 );
 1680                  F &= IF | CF;
 1681                  if ((UINT16)a32 == 0)   F |= ZF | XCF;
 1682                  if (a32 & 0x8000)       F |= SF;
 1683                  if ((a16 ^ 0x8000) & a32 & 0x8000)  F |= VF;
 1684                  if ((a16 ^ a32 ^ 1) & 0x1000)   F |= HF;    //??
 1685                  Cyc(cpustate);
 1686                  break;
 1687  
 1688  
 1689              case DEC:
 1690                  a8 = Read1_8(cpustate) - 1;
 1691                  Write1_8( cpustate, a8 );
 1692                  F = (F & (IF | CF)) | SZHV_dec[a8];
 1693                  if (a8 == 0)    F |= XCF;
 1694                  Cyc(cpustate);
 1695                  break;
 1696              case DECX:
 1697                  if ( F & XCF )
 1698                  {
 1699                      a8 = Read1_8(cpustate) - 1;
 1700                      Write1_8( cpustate, a8 );
 1701                      F = (F & (IF | CF)) | SZHV_dec[a8];
 1702                      if (a8 == 0)    F |= XCF;
 1703                      Cyc(cpustate);
 1704                  }
 1705                  else    Cyc_f(cpustate);
 1706                  break;
 1707              case DEC | OP_16:
 1708                  a16 = Read1_16(cpustate) - 1;
 1709                  Write1_16( cpustate, a16 );
 1710                  if (a16 == 0)   F |=  XCF;
 1711                  else            F &= ~XCF;
 1712                  Cyc(cpustate);
 1713                  break;
 1714              case DECW:
 1715                  a16 = Read1_16(cpustate);
 1716                  a32 = a16 - 1;
 1717                  Write1_16( cpustate, a32 );
 1718                  F = (F & (IF | CF)) | NF;
 1719                  if ((UINT16)a32 == 0)   F |= ZF | XCF;
 1720                  if (a32 & 0x8000)       F |= SF;
 1721                  if (a16 == 0x8000)      F |= VF;
 1722                  if ((a16 ^ a32 ^ 1) & 0x1000)   F |= HF;    //??
 1723                  Cyc(cpustate);
 1724                  break;
 1725  
 1726              case ADD:
 1727              case ADC:
 1728                  a8 = Read1_8(cpustate);
 1729                  b8 = Read2_8(cpustate);
 1730                  a32 = a8 + b8;
 1731                  if ( (cpustate->op == ADC) && (F & CF) )    a32 += 1;
 1732                  Write1_8( cpustate, a32 );
 1733                  F = (F & IF) | SZ[(UINT8)a32];
 1734                  if (a32 & 0x100)            F |= CF | XCF;  //X?
 1735                  if ((a8 ^ a32 ^ b8) & 0x10) F |= HF;
 1736                  if ((b8 ^ a8 ^ 0x80) & (b8 ^ a32) & 0x80)   F |= VF;
 1737                  Cyc(cpustate);
 1738                  break;
 1739              case ADD | OP_16:
 1740              case ADC | OP_16:
 1741                  a16 = Read1_16(cpustate);
 1742                  b16 = Read2_16(cpustate);
 1743                  a32 = a16 + b16;
 1744                  if ( (cpustate->op == (ADC | OP_16)) && (F & CF) )  a32 += 1;
 1745                  Write1_16( cpustate, a32 );
 1746                  if ( (cpustate->op == (ADD | OP_16)) && cpustate->mode2 == MODE_R16 )
 1747                  {
 1748                      F &= SF | ZF | IF | VF;
 1749                  }
 1750                  else
 1751                  {
 1752                      F &= IF;
 1753                      if ((UINT16)a32 == 0)           F |= ZF;
 1754                      if (a32 & 0x8000)               F |= SF;
 1755                      if ((b16 ^ a16 ^ 0x8000) & (b16 ^ a32) & 0x8000)    F |= VF;
 1756                  }
 1757                  if (a32 & 0x10000)              F |= CF | XCF;  //X?
 1758                  if ((a16 ^ a32 ^ b16) & 0x1000) F |= HF;    //??
 1759                  Cyc(cpustate);
 1760                  break;
 1761  
 1762              case CP:
 1763              case SUB:
 1764              case SBC:
 1765                  a8 = Read1_8(cpustate);
 1766                  b8 = Read2_8(cpustate);
 1767                  a32 = a8 - b8;
 1768                  if ( (cpustate->op == SBC) && (F & CF) )    a32 -= 1;
 1769                  F = (F & IF) | SZ[(UINT8)a32] | NF;
 1770                  if (a32 & 0x100)            F |= CF | XCF;  //X?
 1771                  if ((a8 ^ a32 ^ b8) & 0x10) F |= HF;
 1772                  if ((b8 ^ a8) & (a8 ^ a32) & 0x80)  F |= VF;
 1773                  if (cpustate->op != CP)
 1774                      Write1_8( cpustate, a32 );
 1775                  Cyc(cpustate);
 1776                  break;
 1777              case CP | OP_16:
 1778              case SUB | OP_16:
 1779              case SBC | OP_16:
 1780                  a16 = Read1_16(cpustate);
 1781                  b16 = Read2_16(cpustate);
 1782                  a32 = a16 - b16;
 1783                  if ( (cpustate->op == (SBC | OP_16)) && (F & CF) )  a32 -= 1;
 1784                  F = (F & IF) | NF;
 1785                  if ((UINT16)a32 == 0)           F |= ZF;
 1786                  if (a32 & 0x8000)               F |= SF;
 1787                  if (a32 & 0x10000)              F |= CF | XCF;  //X?
 1788                  if ((a16 ^ a32 ^ b16) & 0x1000) F |= HF;    //??
 1789                  if ((b16 ^ a16) & (a16 ^ a32) & 0x8000) F |= VF;
 1790                  if (cpustate->op != (CP | OP_16))
 1791                      Write1_16( cpustate, a32 );
 1792                  Cyc(cpustate);
 1793                  break;
 1794  
 1795              case AND:
 1796                  a8 = Read1_8(cpustate) & Read2_8(cpustate);
 1797                  Write1_8( cpustate, a8 );
 1798                  F = (F & IF) | SZP[a8] | HF;
 1799                  Cyc(cpustate);
 1800                  break;
 1801              case AND | OP_16:
 1802                  a16 = Read1_16(cpustate) & Read2_16(cpustate);
 1803                  Write1_16( cpustate, a16 );
 1804                  F = (F & IF) | HF;
 1805                  if (a16 == 0)       F |= ZF;
 1806                  if (a16 & 0x8000)   F |= SF;
 1807                  Cyc(cpustate);
 1808                  break;
 1809              case XOR:
 1810                  a8 = Read1_8(cpustate) ^ Read2_8(cpustate);
 1811                  Write1_8( cpustate, a8 );
 1812                  F = (F & IF) | SZP[a8];
 1813                  Cyc(cpustate);
 1814                  break;
 1815              case XOR | OP_16:
 1816                  a16 = Read1_16(cpustate) ^ Read2_16(cpustate);
 1817                  Write1_16( cpustate, a16 );
 1818                  F &= IF;
 1819                  if (a16 == 0)       F |= ZF;
 1820                  if (a16 & 0x8000)   F |= SF;
 1821                  Cyc(cpustate);
 1822                  break;
 1823              case OR:
 1824                  a8 = Read1_8(cpustate) | Read2_8(cpustate);
 1825                  Write1_8( cpustate, a8 );
 1826                  F = (F & IF) | SZP[a8];
 1827                  Cyc(cpustate);
 1828                  break;
 1829              case OR | OP_16:
 1830                  a16 = Read1_16(cpustate) | Read2_16(cpustate);
 1831                  Write1_16( cpustate, a16 );
 1832                  F &= IF;
 1833                  if (a16 == 0)       F |= ZF;
 1834                  if (a16 & 0x8000)   F |= SF;
 1835                  Cyc(cpustate);
 1836                  break;
 1837  
 1838              case RLC:
 1839                  a8 = Read1_8(cpustate);
 1840                  a8 = (a8 << 1) | (a8 >> 7);
 1841                  Write1_8( cpustate, a8 );
 1842                  if ( cpustate->mode1 == MODE_R8 && cpustate->r1 == A )  F &= SF | ZF | IF | PF;
 1843                  else                                F = (F & IF) | SZP[a8];
 1844                  if (a8 & 0x01)                      F |= CF | XCF;  // X?
 1845                  Cyc(cpustate);
 1846                  break;
 1847              case RRC:
 1848                  a8 = Read1_8(cpustate);
 1849                  a8 = (a8 >> 1) | (a8 << 7);
 1850                  Write1_8( cpustate, a8 );
 1851                  if ( cpustate->mode1 == MODE_R8 && cpustate->r1 == A )  F &= SF | ZF | IF | PF;
 1852                  else                                F = (F & IF) | SZP[a8];
 1853                  if (a8 & 0x80)                      F |= CF | XCF;  // X?
 1854                  Cyc(cpustate);
 1855                  break;
 1856              case RL:
 1857                  a8 = Read1_8(cpustate);
 1858                  b8 = a8 & 0x80;
 1859                  a8 <<= 1;
 1860                  if (F & CF) a8 |= 0x01;
 1861                  Write1_8( cpustate, a8 );
 1862                  if ( cpustate->mode1 == MODE_R8 && cpustate->r1 == A )  F &= SF | ZF | IF | PF;
 1863                  else                                F = (F & IF) | SZP[a8];
 1864                  if (b8)                             F |= CF | XCF;  // X?
 1865                  Cyc(cpustate);
 1866                  break;
 1867              case RR:
 1868                  a8 = Read1_8(cpustate);
 1869                  b8 = a8 & 0x01;
 1870                  a8 >>= 1;
 1871                  if (F & CF) a8 |= 0x80;
 1872                  Write1_8( cpustate, a8 );
 1873                  if ( cpustate->mode1 == MODE_R8 && cpustate->r1 == A )  F &= SF | ZF | IF | PF;
 1874                  else                                F = (F & IF) | SZP[a8];
 1875                  if (b8)                             F |= CF | XCF;  // X?
 1876                  Cyc(cpustate);
 1877                  break;
 1878  
 1879              case SLA:
 1880              case SLL:
 1881                  a8 = Read1_8(cpustate);
 1882                  b8 = a8 & 0x80;
 1883                  a8 <<= 1;
 1884                  Write1_8( cpustate, a8 );
 1885                  if ( cpustate->mode1 == MODE_R8 && cpustate->r1 == A )  F &= SF | ZF | IF | PF;
 1886                  else                                F = (F & IF) | SZP[a8];
 1887                  if (b8)                             F |= CF | XCF;  // X?
 1888                  Cyc(cpustate);
 1889                  break;
 1890              case SRA:
 1891                  a8 = Read1_8(cpustate);
 1892                  b8 = a8 & 0x01;
 1893                  a8 = (a8 & 0x80) | (a8 >> 1);
 1894                  Write1_8( cpustate, a8 );
 1895                  if ( cpustate->mode1 == MODE_R8 && cpustate->r1 == A )  F &= SF | ZF | IF | PF;
 1896                  else                                F = (F & IF) | SZP[a8];
 1897                  if (b8)                             F |= CF | XCF;  // X?
 1898                  Cyc(cpustate);
 1899                  break;
 1900              case SRL:
 1901                  a8 = Read1_8(cpustate);
 1902                  b8 = a8 & 0x01;
 1903                  a8 >>= 1;
 1904                  Write1_8( cpustate, a8 );
 1905                  if ( cpustate->mode1 == MODE_R8 && cpustate->r1 == A )  F &= SF | ZF | IF | PF;
 1906                  else                                F = (F & IF) | SZP[a8];
 1907                  if (b8)                             F |= CF | XCF;  // X?
 1908                  Cyc(cpustate);
 1909                  break;
 1910              case RLD:
 1911                  a8 = cpustate->af.b.h;
 1912                  b8 = Read1_8(cpustate);
 1913                  Write1_8( cpustate, (b8 << 4) | (a8 & 0x0f) );
 1914                  a8 = (a8 & 0xf0) | (b8 >> 4);
 1915                  F = (F & (IF | CF)) | SZP[a8];
 1916                  cpustate->af.b.h = a8;
 1917                  Cyc(cpustate);
 1918                  break;
 1919              case RRD:
 1920                  a8 = cpustate->af.b.h;
 1921                  b8 = Read1_8(cpustate);
 1922                  Write1_8( cpustate, (b8 >> 4) | (a8 << 4) );
 1923                  a8 = (a8 & 0xf0) | (b8 & 0x0f);
 1924                  F = (F & (IF | CF)) | SZP[a8];
 1925                  cpustate->af.b.h = a8;
 1926                  Cyc(cpustate);
 1927                  break;
 1928  
 1929              case DJNZ:
 1930                  if ( --cpustate->bc.b.h )
 1931                  {
 1932                      cpustate->pc.w.l += /*2 +*/ (INT8)Read1_8(cpustate);
 1933                      Cyc(cpustate);
 1934                  }
 1935                  else    Cyc_f(cpustate);
 1936                  break;
 1937              case DJNZ | OP_16:
 1938                  if ( --cpustate->bc.w.l )
 1939                  {
 1940                      cpustate->pc.w.l += /*2 +*/ (INT8)Read2_8(cpustate);
 1941                      Cyc(cpustate);
 1942                  }
 1943                  else    Cyc_f(cpustate);
 1944                  break;
 1945  
 1946              case MUL:
 1947                  cpustate->hl.w.l = (UINT16)cpustate->hl.b.l * (UINT16)Read2_8(cpustate);
 1948                  Cyc(cpustate);
 1949                  break;
 1950              case DIV:
 1951                  a16 = cpustate->hl.w.l;
 1952                  b16 = (UINT16)Read2_8(cpustate);
 1953                  if (b16 == 0)
 1954                  {
 1955                      F |= VF;
 1956                      cpustate->hl.w.l = (a16 << 8) | ((a16 >> 8) ^ 0xff);
 1957                  }
 1958                  else
 1959                  {
 1960                      cpustate->hl.b.h = a16 % b16;
 1961                      a16 /= b16;
 1962                      if (a16 > 0xff) F |=  VF;
 1963                      else            F &= ~VF;
 1964                      cpustate->hl.b.l = a16;
 1965                  }
 1966                  Cyc(cpustate);
 1967                  break;
 1968  
 1969              default:
 1970                  fatalerror("%04x: unimplemented opcode, op=%02x\n",device->pc(),cpustate->op);
 1971          }
 1972  
 1973          if ( cpustate->op != EI )
 1974              if (cpustate->after_EI)
 1975              {
 1976                  F |= IF;
 1977                  cpustate->after_EI = 0;
 1978              }
 1979  
 1980      } while( cpustate->icount > 0 );
 1981  
 1982      cpustate->icount -= cpustate->extra_cycles;
 1983      cpustate->extra_cycles = 0;
 1984  }
 1985  
 1986  static CPU_RESET( t90 )
 1987  {
 1988      t90_Regs *cpustate = get_safe_token(device);
 1989      cpustate->irq_state = 0;
 1990      cpustate->irq_mask = 0;
 1991      cpustate->pc.d = 0x0000;
 1992      F &= ~IF;
 1993  /*
 1994      P0/D0-D7 P1/A0-A7 P2/A8-A15 P6 P7 = INPUT
 1995      P35/~RD P36/~WR CLK = 1 (ALWAYS OUTPUTS)
 1996      P4/A16-A19 P83 = 0
 1997      dedicated input ports and registers remain unchanged,
 1998      but PC IFF BX BY = 0, A undefined
 1999  */
 2000  }
 2001  
 2002  static CPU_EXIT( t90 )
 2003  {
 2004  }
 2005  
 2006  static CPU_BURN( t90 )
 2007  {
 2008      t90_Regs *cpustate = get_safe_token(device);
 2009      cpustate->icount -= 4 * ((cycles + 3) / 4);
 2010  }
 2011  
 2012  
 2013  /*************************************************************************************************************
 2014  
 2015  
 2016  ----------------------------------------------------------------------------------------------------------------
 2017  FFC0    P0      R/W     Reset   Description
 2018  ----------------------------------------------------------------------------------------------------------------
 2019  7-0     P07-P00 R W     IN      I/O Port 0
 2020  
 2021  ----------------------------------------------------------------------------------------------------------------
 2022  FFC1    P1      R/W     Reset   Description
 2023  ----------------------------------------------------------------------------------------------------------------
 2024  7-0     P17-P10 R W     IN      I/O Port 1
 2025  
 2026  ----------------------------------------------------------------------------------------------------------------
 2027  FFC2    P01CR/  R/W     Reset   Description                 * Prohibit Read-Modify-Write *
 2028          IRFL
 2029  ----------------------------------------------------------------------------------------------------------------
 2030   7      -       -       0       -
 2031   6      IRF0    R       0       INT0    interrupt request (1 = asserted)
 2032   5      IRFT0   R       0       INTT0   ""
 2033   4      IRFT1   R       0       INTT1   ""
 2034   3      -       -       0       -
 2035   2      EXT       W     0       P1/P2 control:  0 = Port                        1 = Address Bus
 2036   1      P1CR      W     0       P1 control:     0 = IN                          1 = OUT     |
 2037   0      P0CR      W     0       P0 control:     0 = IN                          1 = OUT     |
 2038                                                  |                                           |
 2039                              Port 0 also functions as  data bus (D0-D7),so           P1: regardless of <P1CR>
 2040                              P0CR is reset when external memory is accessed          P2: only if P2CR is set to 1 (output)
 2041                                                                                      TMP90C841A: always address bus
 2042  
 2043  ----------------------------------------------------------------------------------------------------------------
 2044  FFC3    IRFH    R/W     Reset   Description                 * Prohibit Read-Modify-Write *
 2045  ----------------------------------------------------------------------------------------------------------------
 2046   7      IRFT2   R W     0       INTT2   interrupt request (1 = asserted)
 2047   6      IRFT3   R W     0       INTT3   ""
 2048   5      IRFT4   R W     0       INTT4   ""
 2049   4      IRF1    R W     0       INT1    ""
 2050   3      IRFT5   R W     0       INTT5   ""
 2051   2      IRF2    R W     0       INT2    ""
 2052   1      IRFRX   R W     0       INTRX   ""
 2053   0      IRFTX   R W     0       INTTX   ""
 2054                    |__ Writing Vector/8 clears the request flip-flop for that interrupt
 2055  
 2056  ----------------------------------------------------------------------------------------------------------------
 2057  FFC4    P2      R/W     Reset   Description
 2058  ----------------------------------------------------------------------------------------------------------------
 2059  7-0     P27-P20 R W     IN      I/O Port 2
 2060  
 2061  ----------------------------------------------------------------------------------------------------------------
 2062  FFC5    P2CR    R/W     Reset   Description
 2063  ----------------------------------------------------------------------------------------------------------------
 2064  7-0     P27C-     W     0       Port 2 control: 0 = IN                          1 = OUT
 2065          P20C
 2066  
 2067  ----------------------------------------------------------------------------------------------------------------
 2068  FFC6    P3      R/W     Reset   Description
 2069  ----------------------------------------------------------------------------------------------------------------
 2070   7      P37     R       IN      P37 input
 2071   6      P36     R W     1       ~WD
 2072   5      P35     R W     1       ~RD
 2073   4      P34     R       IN      P34 input
 2074   3      P33     R W     1       TxD / P33 output
 2075   2      P32     R W     1       TxD / P32 output
 2076   1      P31     R       IN      RxD / P31 input
 2077   0      P30     R       IN      RxD / P30 input
 2078  
 2079  ----------------------------------------------------------------------------------------------------------------
 2080  FFC7    P3CR    R/W     Reset   Description             * Prohibit Read-Modify-Write *
 2081  ----------------------------------------------------------------------------------------------------------------
 2082  7-6     WAITC1-0R W     00      Wait control:   00 = 2state     01 = normal     10 = no wait    11 = reserved
 2083   5      RDE     R W     0       RD control:     0 = only external access        1 = always
 2084   4      ODE     R W     0       P33 control:    0 = CMOS                        1 = Open Drain
 2085  3-2     TXDC1-0 R W     00      P33-P32:        00 = OUT-OUT    01 = OUT-TxD    10 = TxD-OUT    11 = TxD-~RTS/SCLK
 2086  1-0     RXDC1-0 R W     00      P31-P30:        00 = IN-IN      01 = IN-RxD     10 = RxD-IN     11 = not used
 2087  
 2088  ----------------------------------------------------------------------------------------------------------------
 2089  FFC8    P4      R/W     Reset   Description
 2090  ----------------------------------------------------------------------------------------------------------------
 2091  7-4     -
 2092  3-0     P43-P40 R W     0       I/O Port 4 bits 3-0 or address bus A16-A19
 2093  
 2094  ----------------------------------------------------------------------------------------------------------------
 2095  FFC9    P4CR    R/W     Reset   Description
 2096  ----------------------------------------------------------------------------------------------------------------
 2097  7-4     -
 2098  3-0     P43C-     W     0       Port 4 control: 0 = OUT                         1 = Address Output
 2099          P40C
 2100  
 2101  ----------------------------------------------------------------------------------------------------------------
 2102  FFCA    P5      R/W     Reset   Description
 2103  ----------------------------------------------------------------------------------------------------------------
 2104  7       -       R       0       Test bit, must be set to 0
 2105  6       -       R       0
 2106  5-0     P55-P50 R       0       I/O Port 5 bits 5-0 / AN5-AN0 analog inputs
 2107  
 2108  ----------------------------------------------------------------------------------------------------------------
 2109  FFCB    SMMOD   R/W     Reset   Description
 2110  ----------------------------------------------------------------------------------------------------------------
 2111   7      -       R W     -
 2112   6      SM7M0   R W     0       Motor Step:         0 = Full                        1 = Half
 2113   5      P70C1   R W     0       Port 7 control:     0 = IN-OUT      0 = IN-OUT,TO3  1 = IN / M1     1 = Timer 4
 2114   4      P70C0   R W     0                           0               1               0   Timer 2,3   1
 2115   3      -       R W     -
 2116   2      SM6M0   R W     0       Motor Step:         0 = Full                        1 = Half
 2117   1      P60C1   R W     0       Port 6 control:     0 = IN-OUT      0 = IN-OUT,TO1  1 = IN / M0
 2118   0      P60C0   R W     0                           0               1               X   Timer 0,1
 2119  
 2120  ----------------------------------------------------------------------------------------------------------------
 2121  FFCC    P6      R/W     Reset   Description             * Read-Modify-Write not available in Stepping Motor control *
 2122  ----------------------------------------------------------------------------------------------------------------
 2123  7-4     SA60-63   W     Undef   Stepping motor Port 0 (M0) Shifter alternate reg.
 2124  3-0     P63-P60 R W     IN      Bits 3-0 of I/O Port 6 or Stepping motor Port 0 (M0)
 2125  
 2126  ----------------------------------------------------------------------------------------------------------------
 2127  FFCD    P7      R/W     Reset   Description             * Read-Modify-Write not available in Stepping Motor control *
 2128  ----------------------------------------------------------------------------------------------------------------
 2129  7-4     SA70-73   W     Undef   Stepping motor Port 1 (M1) Shifter alternate reg.
 2130  3-0     P73-P70 R W     IN      Bits 3-0 of I/O Port 7 or Stepping motor Port 1 (M1)
 2131  
 2132  ----------------------------------------------------------------------------------------------------------------
 2133  FFCE    P67CR   R/W     Reset   Description             * Prohibit Read-Modify-Write *
 2134  ----------------------------------------------------------------------------------------------------------------
 2135  7-4     P73-70C   W     0       Port 7:             0 = IN                          1 = OUT
 2136  3-0     P63-60C   W     0       Port 6:             0 = IN                          1 = OUT
 2137  
 2138  ----------------------------------------------------------------------------------------------------------------
 2139  FFD0    P8      R/W     Reset   Description
 2140  ----------------------------------------------------------------------------------------------------------------
 2141  7-4     -
 2142   3      P83     R W     0       P83 / TIO3 / TIO4 output
 2143   2      P82     R       IN      P82 + INT2 input
 2144   1      P81     R       IN      P81 + INT1 input
 2145   0      P80     R       IN      P80 + INT0 input
 2146  
 2147  ----------------------------------------------------------------------------------------------------------------
 2148  FFD1    P8CR    R/W     Reset   Description
 2149  ----------------------------------------------------------------------------------------------------------------
 2150  7-4     -
 2151   3      P83OC     W     0       P83 out control:    0 = P83                         1 = TO3 / TO4
 2152   2      ZCE2      W     0       INT2/TI5 control:   0 = ZCD disable                 1 = ZCD enable
 2153   1      ZCE1      W     0       INT1/TI4 control:   0 = ZCD disable                 1 = ZCD enable
 2154   0      EDGE      W     0       INT0 control:       0 = Level                       1 = Rising edge
 2155  
 2156  ----------------------------------------------------------------------------------------------------------------
 2157  FFD2    WDMOD   R/W     Reset   Description
 2158  ----------------------------------------------------------------------------------------------------------------
 2159   7      WDTE    R W     1       1 = WDT Enable
 2160   6      WDTP1   R W     0       WDT detection time: 0 = 2^14/fc     0 = 2^16/fc     1 = 2^18/fc     1 = 2^20/fc
 2161   5      WDTP0   R W     0                           0               1               0               1
 2162   4      WARM    R W     0       Warming up time:    0 = 2^14/fc                     1 = 2^16/fc
 2163   3      HALTM1  R W     0       Standby mode:       0 = RUN         0 = STOP        1 = IDLE1       1 = IDLE2
 2164   2      HALTM0  R W     0                           0               1               0               1
 2165   1      EXF     R       Undef   Invert each time EXX instruction is executed
 2166   0      DRIVE   R W     0       1 to drive pins in stop mode
 2167  
 2168  ----------------------------------------------------------------------------------------------------------------
 2169  FFD4    TREG0   R/W     Reset   Description
 2170  ----------------------------------------------------------------------------------------------------------------
 2171  7-0     -       W       0       Timer 0 match value
 2172  
 2173  ----------------------------------------------------------------------------------------------------------------
 2174  FFD5    TREG1   R/W     Reset   Description
 2175  ----------------------------------------------------------------------------------------------------------------
 2176  7-0     -       W       0       Timer 0 match value
 2177  
 2178  ----------------------------------------------------------------------------------------------------------------
 2179  FFD6    TREG2   R/W     Reset   Description
 2180  ----------------------------------------------------------------------------------------------------------------
 2181  7-0     -       W       0       Timer 0 match value
 2182  
 2183  ----------------------------------------------------------------------------------------------------------------
 2184  FFD7    TREG3   R/W     Reset   Description
 2185  ----------------------------------------------------------------------------------------------------------------
 2186  7-0     -       W       0       Timer 0 match value
 2187  
 2188  ----------------------------------------------------------------------------------------------------------------
 2189  FFD8    TCLK    R/W     Reset   Description
 2190  ----------------------------------------------------------------------------------------------------------------
 2191  7-6     T3CLK1-0R W     00      Timer 3 clock:      00 = Timer 2    01 = clock      10 = clock/16   11 = clock/256  <- Timer 2 overflow output in 16 bit mode
 2192  5-4     T2CLK1-0R W     00      Timer 2 clock:      00 = -          01 = clock      10 = clock/16   11 = clock/256
 2193  3-2     T1CLK1-0R W     00      Timer 1 clock:      00 = Timer 0    01 = clock      10 = clock/16   11 = clock/256  <- Timer 0 overflow output in 16 bit mode
 2194  1-0     T0CLK1-0R W     00      Timer 0 clock:      00 = -          01 = clock      10 = clock/16   11 = clock/256
 2195  
 2196  ----------------------------------------------------------------------------------------------------------------
 2197  FFD9    TFFCR   R/W     Reset   Description
 2198  ----------------------------------------------------------------------------------------------------------------
 2199  7-6     TFF3C1-0  W     -       Timer 3 flip-flop:  00 = Clear      01 = Set        10 = Invert     11 = Don't care <-  Always read as 11
 2200  5       TFF3IE  R W     0       Timer 3 Invert:     0 = Disable                     1 = Enable
 2201  4       TFF3IS  R W     0       Timer 3 Invert:     0 = Timer 2                     1 = Timer 3
 2202  3-2     TFF1C1-0  W     -       Timer 1 Flip-Flop:  00 = Clear      01 = Set        10 = Invert     11 = Don't care <-  Always read as 11
 2203  1       TFF1IE  R W     0       Timer 1 Invert:     0 = Disable                     1 = Enable
 2204  0       TFF1IS  R W     0       Timer 1 Invert:     0 = Timer 0                     1 = Timer 1
 2205  
 2206  ----------------------------------------------------------------------------------------------------------------
 2207  FFDA    TMOD    R/W     Reset   Description
 2208  ----------------------------------------------------------------------------------------------------------------
 2209  7-6     T32M1-0 R W     00      Timers 2 & 3:       00 = 8b x 2     01 = 16b(T3+T2) 10 = 8b PPG(T3) 11 = 8b PWM (T3) + 8b (T2)
 2210  5-4     PWM21-0 R W     00      Timer 3 PWM freq:   00 = -          01 = 63/fc      10 = 127/fc     11 = 255/fc
 2211  3-2     T10M1-0 R W     00      Timers 1 & 0:       00 = 8b x 2     01 = 16b(T1+T0) 10 = 8b PPG(T1) 11 = 8b PWM (T1) + 8b (T0)
 2212  1-0     PWM01-0 R W     00      Timer 1 PWM freq:   00 = -          01 = 63/fc      10 = 127/fc     11 = 255/fc
 2213  
 2214  ----------------------------------------------------------------------------------------------------------------
 2215  FFDB    TRUN    R/W     Reset   Description
 2216  ----------------------------------------------------------------------------------------------------------------
 2217  7-6     BRATE1-0R W     00      Serial baud rate:   00 = 300/150    01 = 1200/600   10 = 4800/2400  11 = 19200/9600
 2218   5      PRRUN   R W     0       Prescaler control:  0 = Stop & Clear                1 = Run
 2219   4      T4RUN   R W     0       Timer 4 control:    0 = Stop & Clear                1 = Run
 2220  3-0     T4RUN-0 R W     00      Timers 3-0 control: 0 = Stop & Clear                1 = Run
 2221  
 2222  ----------------------------------------------------------------------------------------------------------------
 2223  FFE6    INTEL   R/W     Reset   Description
 2224  ----------------------------------------------------------------------------------------------------------------
 2225   7      DET2    R W     0       INTT2/INTAD interrupt enable flag (1 = enable)
 2226   6      DET3    R W     0       INTT3       ""
 2227   5      DET4    R W     0       INTT4       ""
 2228   4      DE1     R W     0       INT1        ""
 2229   3      DET5    R W     0       INTT5       ""
 2230   2      DE2     R W     0       INT2        ""
 2231   1      DERX    R W     0       INTRX       ""
 2232   0      DETX    R W     0       INTTX       ""
 2233  
 2234  ----------------------------------------------------------------------------------------------------------------
 2235  FFE7    INTEH   R/W     Reset   Description
 2236  ----------------------------------------------------------------------------------------------------------------
 2237   7      -       R W     0       Write "0"
 2238   6      DE0     R W     0       INT0        DMA enable flag (1 = enable)
 2239   5      DET0    R W     0       INTT0       ""
 2240   4      DET1    R W     0       INTT1       ""
 2241   3      ADIS    R W     0       INTT2/INTAD selection (1 = INTAD)
 2242   2      IE0     R W     0       INT0        interrupt enable flag (1 = enable)
 2243   1      IET0    R W     0       INTT0       ""
 2244   0      IET1    R W     0       INTT1       ""
 2245  
 2246  ----------------------------------------------------------------------------------------------------------------
 2247  FFE8    DMAEH   R/W     Reset   Description
 2248  ----------------------------------------------------------------------------------------------------------------
 2249   7      DET2    R W     0       INTT2/INTAD DMA enable flag (1 = enable)
 2250   6      DET3    R W     0       INTT3       ""
 2251   5      DET4    R W     0       INTT4       ""
 2252   4      DE1     R W     0       INT1        ""
 2253   3      DET5    R W     0       INTT5       ""
 2254   2      DE2     R W     0       INT2        ""
 2255   1      DERX    R W     0       INTRX       ""
 2256   0      DETX    R W     0       INTTX       ""
 2257  
 2258  ----------------------------------------------------------------------------------------------------------------
 2259  FFEC    BX      R/W     Reset   Description
 2260  ----------------------------------------------------------------------------------------------------------------
 2261   7      -       R       1
 2262   6      -       R       1
 2263   5      -       R       1
 2264   4      -       R       1
 2265   3      BX3     R W     0       IX bank register bit 3
 2266   2      BX2     R W     0       IX bank register bit 2
 2267   1      BX1     R w     0       IX bank register bit 1
 2268   0      BX0     R W     0       IX bank register bit 0
 2269  
 2270  ----------------------------------------------------------------------------------------------------------------
 2271  FFED    BX      R/W     Reset   Description
 2272  ----------------------------------------------------------------------------------------------------------------
 2273   7      -       R       1
 2274   6      -       R       1
 2275   5      -       R       1
 2276   4      -       R       1
 2277   3      BY3     R W     0       IY bank register bit 3
 2278   2      BY2     R W     0       IY bank register bit 2
 2279   1      BY1     R w     0       IY bank register bit 1
 2280   0      BY0     R W     0       IY bank register bit 0
 2281  
 2282  *************************************************************************************************************/
 2283  
 2284  static READ8_HANDLER( t90_internal_registers_r )
 2285  {
 2286      t90_Regs *cpustate = get_safe_token(&space.device());
 2287  
 2288      #define RIO     cpustate->io->read_byte( T90_IOBASE+offset )
 2289  
 2290      UINT8 data = cpustate->internal_registers[offset];
 2291      switch ( T90_IOBASE + offset )
 2292      {
 2293          case T90_P3:    // 7,4,1,0
 2294              return (data & 0x6c) | (RIO & 0x93);
 2295  
 2296          case T90_P4:    // only output
 2297              return data & 0x0f;
 2298  
 2299          case T90_P5:
 2300              return (RIO & 0x3f);
 2301  
 2302          case T90_P6:
 2303          case T90_P7:
 2304              return (data & 0xf0) | (RIO & 0x0f);
 2305  
 2306          case T90_P8:    // 2,1,0
 2307              return (data & 0x08) | (RIO & 0x07);
 2308  
 2309          case T90_BX:
 2310          case T90_BY:
 2311              return 0xf0 | data;
 2312      }
 2313      return data;
 2314  }
 2315  
 2316  static void t90_start_timer(t90_Regs *cpustate, int i)
 2317  {
 2318      int prescaler;
 2319      attotime period;
 2320  
 2321      cpustate->timer_value[i] = 0;
 2322  
 2323      switch((cpustate->internal_registers[ T90_TMOD - T90_IOBASE ] >> (i * 2)) & 0x03)
 2324      {
 2325          case 0:
 2326              // 8-bit mode
 2327              break;
 2328          case 1:
 2329              // 16-bit mode
 2330              if (i & 1)
 2331              {
 2332                  logerror("%04X: CPU Timer %d clocked by Timer %d overflow signal\n", cpustate->pc.w.l, i,i-1);
 2333                  return;
 2334              }
 2335              break;
 2336          case 2:
 2337              logerror("%04X: CPU Timer %d, unsupported PPG mode\n", cpustate->pc.w.l, i);
 2338              return;
 2339          case 3:
 2340              logerror("%04X: CPU Timer %d, unsupported PWM mode\n", cpustate->pc.w.l, i);
 2341              return;
 2342      }
 2343  
 2344      switch((cpustate->internal_registers[ T90_TCLK - T90_IOBASE ] >> (i * 2)) & 0x03)
 2345      {
 2346          case 0: if (i & 1)  logerror("%04X: CPU Timer %d clocked by Timer %d match signal\n", cpustate->pc.w.l, i,i-1);
 2347                  else        logerror("%04X: CPU Timer %d, unsupported TCLK = 0\n", cpustate->pc.w.l, i);
 2348                  return;
 2349          case 2: prescaler =  16;    break;
 2350          case 3: prescaler = 256;    break;
 2351          default:
 2352          case 1: prescaler =   1;    break;
 2353      }
 2354  
 2355  
 2356      period = cpustate->timer_period * prescaler;
 2357  
 2358      cpustate->timer[i]->adjust(period, i, period);
 2359  
 2360      logerror("%04X: CPU Timer %d started at %lf Hz\n", cpustate->pc.w.l, i, 1.0 / period.as_double());
 2361  }
 2362  
 2363  static void t90_start_timer4(t90_Regs *cpustate)
 2364  {
 2365      int prescaler;
 2366      attotime period;
 2367  
 2368      cpustate->timer4_value = 0;
 2369  
 2370      switch(cpustate->internal_registers[ T90_T4MOD - T90_IOBASE ] & 0x03)
 2371      {
 2372          case 1:     prescaler =   1;    break;
 2373          case 2:     prescaler =  16;    break;
 2374          default:    logerror("%04X: CPU Timer 4, unsupported T4MOD = %d\n", cpustate->pc.w.l,cpustate->internal_registers[ T90_T4MOD - T90_IOBASE ] & 0x03);
 2375                      return;
 2376      }
 2377  
 2378      period = cpustate->timer_period * prescaler;
 2379  
 2380      cpustate->timer[4]->adjust(period, 4, period);
 2381  
 2382      logerror("%04X: CPU Timer 4 started at %lf Hz\n", cpustate->pc.w.l, 1.0 / period.as_double());
 2383  }
 2384  
 2385  
 2386  static void t90_stop_timer(t90_Regs *cpustate, int i)
 2387  {
 2388      cpustate->timer[i]->adjust(attotime::never, i);
 2389      logerror("%04X: CPU Timer %d stopped\n", cpustate->pc.w.l, i);
 2390  }
 2391  
 2392  static void t90_stop_timer4(t90_Regs *cpustate)
 2393  {
 2394      t90_stop_timer(cpustate, 4);
 2395  }
 2396  
 2397  static TIMER_CALLBACK( t90_timer_callback )
 2398  {
 2399      t90_Regs *cpustate = (t90_Regs *)ptr;
 2400      int is16bit;
 2401      int i = param;
 2402  
 2403      if ( (cpustate->internal_registers[ T90_TRUN - T90_IOBASE ] & (1 << i)) == 0 )
 2404          return;
 2405  
 2406  //  logerror("CPU Timer %d fired! value = %d\n", i,(unsigned)cpustate->timer_value[i]);
 2407  
 2408      cpustate->timer_value[i]++;
 2409  
 2410      is16bit = ((cpustate->internal_registers[ T90_TMOD - T90_IOBASE ] >> (i/2 * 2 + 2)) & 0x03) == 1;
 2411  
 2412      // Match
 2413  
 2414      if ( cpustate->timer_value[i] == cpustate->internal_registers[ T90_TREG0+i - T90_IOBASE ] )
 2415      {
 2416  //      logerror("CPU Timer %d match\n", i);
 2417  
 2418          if (is16bit)
 2419          {
 2420              if (i & 1)
 2421              {
 2422                  if ( cpustate->timer_value[i-1] == cpustate->internal_registers[ T90_TREG0+i-1 - T90_IOBASE ] )
 2423                  {
 2424                      cpustate->timer_value[i]   = 0;
 2425                      cpustate->timer_value[i-1] = 0;
 2426  
 2427                      set_irq_line(cpustate, INTT0 + i, 1);
 2428                  }
 2429              }
 2430              else
 2431                  set_irq_line(cpustate, INTT0 + i, 1);
 2432          }
 2433          else
 2434          {
 2435              cpustate->timer_value[i] = 0;
 2436              set_irq_line(cpustate, INTT0 + i, 1);
 2437          }
 2438  
 2439          switch (i)
 2440          {
 2441              case 0:
 2442              case 2:
 2443                  if ( !is16bit )
 2444                      if ( (cpustate->internal_registers[ T90_TCLK - T90_IOBASE ] & (0x03 << (i * 2 + 2))) == 0 ) // T0/T1 match signal clocks T1/T3
 2445                          t90_timer_callback(machine, cpustate, i+1);
 2446                  break;
 2447          }
 2448      }
 2449  
 2450      // Overflow
 2451  
 2452      if ( cpustate->timer_value[i] == 0 )
 2453      {
 2454  //      logerror("CPU Timer %d overflow\n", i);
 2455  
 2456          switch (i)
 2457          {
 2458              case 0:
 2459              case 2:
 2460                  if ( is16bit )  // T0/T1 overflow signal clocks T1/T3
 2461                      t90_timer_callback(machine, cpustate, i+1);
 2462                  break;
 2463          }
 2464      }
 2465  }
 2466  
 2467  static TIMER_CALLBACK( t90_timer4_callback )
 2468  {
 2469  //  logerror("CPU Timer 4 fired! value = %d\n", (unsigned)cpustate->timer_value[4]);
 2470  
 2471      t90_Regs *cpustate = (t90_Regs *)ptr;
 2472      cpustate->timer4_value++;
 2473  
 2474      // Match
 2475  
 2476      if ( cpustate->timer4_value == (cpustate->internal_registers[ T90_TREG4L - T90_IOBASE ] + (cpustate->internal_registers[ T90_TREG4H - T90_IOBASE ] << 8)) )
 2477      {
 2478  //      logerror("CPU Timer 4 matches TREG4\n");
 2479          set_irq_line(cpustate, INTT4, 1);
 2480      }
 2481      if ( cpustate->timer4_value == (cpustate->internal_registers[ T90_TREG5L - T90_IOBASE ] + (cpustate->internal_registers[ T90_TREG5H - T90_IOBASE ] << 8)) )
 2482      {
 2483  //      logerror("CPU Timer 4 matches TREG5\n");
 2484          set_irq_line(cpustate, INTT5, 1);
 2485          if (cpustate->internal_registers[ T90_T4MOD - T90_IOBASE ] & 0x04)
 2486              cpustate->timer4_value = 0;
 2487      }
 2488  
 2489      // Overflow
 2490  
 2491      if ( cpustate->timer_value == 0 )
 2492      {
 2493  //      logerror("CPU Timer 4 overflow\n");
 2494      }
 2495  }
 2496  
 2497  static WRITE8_HANDLER( t90_internal_registers_w )
 2498  {
 2499      #define WIO     cpustate->io->write_byte( T90_IOBASE+offset, data )
 2500  
 2501      t90_Regs *cpustate = get_safe_token(&space.device());
 2502      UINT8 out_mask;
 2503      UINT8 old = cpustate->internal_registers[offset];
 2504      switch ( T90_IOBASE + offset )
 2505      {
 2506          case T90_TRUN:
 2507          {
 2508              int i;
 2509              // Timers 0-3
 2510              for (i = 0; i < 4; i++)
 2511              {
 2512                  if ( (old ^ data) & (0x20 | (1 << i)) ) // if timer bit or prescaler bit changed
 2513                  {
 2514                      if ( data == (0x20 | (1 << i)) )    t90_start_timer(cpustate, i);
 2515                      else                                t90_stop_timer(cpustate, i);
 2516                  }
 2517              }
 2518              // Timer 4
 2519              if ( (old ^ data) & (0x20 | 0x10) )
 2520              {
 2521                  if ( data == (0x20 | 0x10) )    t90_start_timer4(cpustate);
 2522                  else                            t90_stop_timer4(cpustate);
 2523              }
 2524              break;
 2525          }
 2526  
 2527          case T90_INTEL:
 2528              cpustate->irq_mask  &=  ~(  (1 << INTT2 ) |
 2529                                      (1 << INTT3 ) |
 2530                                      (1 << INTT4 ) |
 2531                                      (1 << INT1  ) |
 2532                                      (1 << INTT5 ) |
 2533                                      (1 << INT2  ) |
 2534                                      (1 << INTRX ) |
 2535                                      (1 << INTTX )   );
 2536  
 2537              cpustate->irq_mask  |=  ((data & 0x80) ? (1 << INTT2 ) : 0) |
 2538                                  ((data & 0x40) ? (1 << INTT3 ) : 0) |
 2539                                  ((data & 0x20) ? (1 << INTT4 ) : 0) |
 2540                                  ((data & 0x10) ? (1 << INT1  ) : 0) |
 2541                                  ((data & 0x08) ? (1 << INTT5 ) : 0) |
 2542                                  ((data & 0x04) ? (1 << INT2  ) : 0) |
 2543                                  ((data & 0x02) ? (1 << INTRX ) : 0) |
 2544                                  ((data & 0x01) ? (1 << INTTX ) : 0) ;
 2545              break;
 2546  
 2547          case T90_INTEH:
 2548              cpustate->irq_mask  &=  ~(  (1 << INT0 ) |
 2549                                      (1 << INTT0) |
 2550                                      (1 << INTT1)    );
 2551  
 2552              cpustate->irq_mask  |=  ((data & 0x04) ? (1 << INT0 ) : 0) |
 2553                                  ((data & 0x02) ? (1 << INTT0) : 0) |
 2554                                  ((data & 0x01) ? (1 << INTT1) : 0) ;
 2555              break;
 2556  
 2557          case T90_P3:
 2558              data &= 0x6c;
 2559              WIO;
 2560              break;
 2561  
 2562          case T90_P4:
 2563              data &= 0x0f;
 2564              out_mask = (~cpustate->internal_registers[ T90_P4CR - T90_IOBASE ]) & 0x0f;
 2565              if (out_mask)
 2566              {
 2567                  data &= out_mask;
 2568                  WIO;
 2569              }
 2570              break;
 2571  
 2572          case T90_P6:
 2573              out_mask = cpustate->internal_registers[ T90_P67CR - T90_IOBASE ] & 0x0f;
 2574              switch (cpustate->internal_registers[ T90_SMMOD - T90_IOBASE ] & 0x03)
 2575              {
 2576                  case 1:
 2577                      data &= ~0x01;
 2578                      // add TO1 here
 2579                      break;
 2580                  case 2:
 2581                  case 3:
 2582                      data &= ~0x0f;
 2583                      // add M0 here
 2584                      break;
 2585              }
 2586  
 2587              if (out_mask)
 2588              {
 2589                  data &= out_mask;
 2590                  WIO;
 2591              }
 2592              break;
 2593  
 2594          case T90_P7:
 2595              out_mask = (cpustate->internal_registers[ T90_P67CR - T90_IOBASE ] & 0xf0) >> 4;
 2596              switch ((cpustate->internal_registers[ T90_SMMOD - T90_IOBASE ]>>4) & 0x03)
 2597              {
 2598                  case 1:
 2599                      data &= ~0x01;
 2600                      // add TO3 here
 2601                      break;
 2602                  case 2:
 2603                  case 3:
 2604                      data &= ~0x0f;
 2605                      // add M1 here
 2606                      break;
 2607              }
 2608  
 2609              if (out_mask)
 2610              {
 2611                  data &= out_mask;
 2612                  WIO;
 2613              }
 2614              break;
 2615  
 2616          case T90_P8:
 2617              data &= 0x0f;
 2618              out_mask = (~cpustate->internal_registers[ T90_P8CR - T90_IOBASE ]) & 0x08;
 2619              if (out_mask)
 2620              {
 2621                  data &= out_mask;
 2622                  WIO;
 2623              }
 2624              break;
 2625  
 2626          case T90_BX:
 2627              cpustate->ixbase = (data & 0xf) << 16;
 2628              break;
 2629          case T90_BY:
 2630              cpustate->iybase = (data & 0xf) << 16;
 2631              break;
 2632      }
 2633      cpustate->internal_registers[offset] = data;
 2634  }
 2635  
 2636  static void state_register( legacy_cpu_device *device )
 2637  {
 2638      t90_Regs *cpustate = get_safe_token(device);
 2639  
 2640      device->save_item(NAME(cpustate->prvpc.w.l));
 2641      device->save_item(NAME(cpustate->pc.w.l));
 2642      device->save_item(NAME(cpustate->sp.w.l));
 2643      device->save_item(NAME(cpustate->af.w.l));
 2644      device->save_item(NAME(cpustate->bc.w.l));
 2645      device->save_item(NAME(cpustate->de.w.l));
 2646      device->save_item(NAME(cpustate->hl.w.l));
 2647      device->save_item(NAME(cpustate->ix.w.l));
 2648      device->save_item(NAME(cpustate->iy.w.l));
 2649      device->save_item(NAME(cpustate->af2.w.l));
 2650      device->save_item(NAME(cpustate->bc2.w.l));
 2651      device->save_item(NAME(cpustate->de2.w.l));
 2652      device->save_item(NAME(cpustate->hl2.w.l));
 2653      device->save_item(NAME(cpustate->halt));
 2654      device->save_item(NAME(cpustate->after_EI));
 2655      device->save_item(NAME(cpustate->irq_state));
 2656      device->save_item(NAME(cpustate->irq_mask));
 2657      device->save_item(NAME(cpustate->icount));
 2658      device->save_item(NAME(cpustate->extra_cycles));
 2659  
 2660      device->save_item(NAME(cpustate->internal_registers));
 2661      device->save_item(NAME(cpustate->ixbase));
 2662      device->save_item(NAME(cpustate->iybase));
 2663  
 2664      device->save_item(NAME(cpustate->timer_value));
 2665      device->save_item(NAME(cpustate->timer4_value));
 2666  
 2667      // Work registers
 2668      device->save_item(NAME(cpustate->op));
 2669      device->save_item(NAME(cpustate->mode1));
 2670      device->save_item(NAME(cpustate->r1));
 2671      device->save_item(NAME(cpustate->r1b));
 2672      device->save_item(NAME(cpustate->mode2));
 2673      device->save_item(NAME(cpustate->r2));
 2674      device->save_item(NAME(cpustate->r2b));
 2675  
 2676      device->save_item(NAME(cpustate->cyc_t));
 2677      device->save_item(NAME(cpustate->cyc_f));
 2678      device->save_item(NAME(cpustate->addr));
 2679  }
 2680  
 2681  
 2682  static CPU_INIT( t90 )
 2683  {
 2684      t90_Regs *cpustate = get_safe_token(device);
 2685      int i, p;
 2686  
 2687      state_register(device);
 2688  
 2689      for (i = 0; i < 256; i++)
 2690      {
 2691          p = 0;
 2692          if( i&0x01 ) ++p;
 2693          if( i&0x02 ) ++p;
 2694          if( i&0x04 ) ++p;
 2695          if( i&0x08 ) ++p;
 2696          if( i&0x10 ) ++p;
 2697          if( i&0x20 ) ++p;
 2698          if( i&0x40 ) ++p;
 2699          if( i&0x80 ) ++p;
 2700          SZ[i] = i ? i & SF : ZF;
 2701  //      SZ[i] |= (i & (YF | XF));       /* undocumented flag bits 5+3 */
 2702          SZ_BIT[i] = i ? i & SF : ZF | PF;
 2703  //      SZ_BIT[i] |= (i & (YF | XF));   /* undocumented flag bits 5+3 */
 2704          SZP[i] = SZ[i] | ((p & 1) ? 0 : PF);
 2705          SZHV_inc[i] = SZ[i];
 2706          if( i == 0x80 ) SZHV_inc[i] |= VF;
 2707          if( (i & 0x0f) == 0x00 ) SZHV_inc[i] |= HF;
 2708          SZHV_dec[i] = SZ[i] | NF;
 2709          if( i == 0x7f ) SZHV_dec[i] |= VF;
 2710          if( (i & 0x0f) == 0x0f ) SZHV_dec[i] |= HF;
 2711      }
 2712  
 2713      memset(cpustate, 0, sizeof(t90_Regs));
 2714      cpustate->irq_callback = irqcallback;
 2715      cpustate->device = device;
 2716      cpustate->program = &device->space(AS_PROGRAM);
 2717      cpustate->io = &device->space(AS_IO);
 2718  
 2719      cpustate->timer_period = attotime::from_hz(device->unscaled_clock()) * 8;
 2720  
 2721      // Reset registers to their initial values
 2722  
 2723  //  IX = IY = 0xffff;
 2724  //  F = ZF;
 2725  
 2726      // Timers
 2727  
 2728      for (i = 0; i < 4; i++)
 2729          cpustate->timer[i] = device->machine().scheduler().timer_alloc(FUNC(t90_timer_callback), cpustate);
 2730  
 2731      cpustate->timer[4] = device->machine().scheduler().timer_alloc(FUNC(t90_timer4_callback), cpustate);
 2732  }
 2733  
 2734  static ADDRESS_MAP_START(tmp90840_mem, AS_PROGRAM, 8, legacy_cpu_device)
 2735      AM_RANGE(   0x0000,     0x1fff          )   AM_ROM  // 8KB ROM (internal)
 2736      AM_RANGE(   0xfec0,     0xffc0          )   AM_RAM  // 256b RAM (internal)
 2737      AM_RANGE(   T90_IOBASE, T90_IOBASE+47   )   AM_READWRITE_LEGACY( t90_internal_registers_r, t90_internal_registers_w )
 2738  ADDRESS_MAP_END
 2739  static ADDRESS_MAP_START(tmp90841_mem, AS_PROGRAM, 8, legacy_cpu_device)
 2740  //  AM_RANGE(   0x0000,     0x1fff          )   AM_ROM  // rom-less
 2741      AM_RANGE(   0xfec0,     0xffc0          )   AM_RAM  // 256b RAM (internal)
 2742      AM_RANGE(   T90_IOBASE, T90_IOBASE+47   )   AM_READWRITE_LEGACY( t90_internal_registers_r, t90_internal_registers_w )
 2743  ADDRESS_MAP_END
 2744  
 2745  static ADDRESS_MAP_START(tmp91640_mem, AS_PROGRAM, 8, legacy_cpu_device )
 2746      AM_RANGE(   0x0000,     0x3fff          ) AM_ROM    // 16KB ROM (internal)
 2747      AM_RANGE(   0xfdc0,     0xffc0          ) AM_RAM    // 512b RAM (internal)
 2748      AM_RANGE(   T90_IOBASE, T90_IOBASE+47   ) AM_READWRITE_LEGACY( t90_internal_registers_r, t90_internal_registers_w )
 2749  ADDRESS_MAP_END
 2750  static ADDRESS_MAP_START(tmp91641_mem, AS_PROGRAM, 8, legacy_cpu_device )
 2751  //  AM_RANGE(   0x0000,     0x3fff          ) AM_ROM    // rom-less
 2752      AM_RANGE(   0xfdc0,     0xffc0          ) AM_RAM    // 512b RAM (internal)
 2753      AM_RANGE(   T90_IOBASE, T90_IOBASE+47   ) AM_READWRITE_LEGACY( t90_internal_registers_r, t90_internal_registers_w )
 2754  ADDRESS_MAP_END
 2755  
 2756  static CPU_SET_INFO( t90 )
 2757  {
 2758      t90_Regs *cpustate = get_safe_token(device);
 2759  
 2760      switch (state)
 2761      {
 2762          /* --- the following bits of info are set as 64-bit signed integers --- */
 2763  
 2764          case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI:      set_irq_line(cpustate, INTNMI, info->i);                break;
 2765          case CPUINFO_INT_INPUT_STATE + INPUT_LINE_IRQ0:     set_irq_line(cpustate, INT0,   info->i);                break;
 2766          case CPUINFO_INT_INPUT_STATE + INPUT_LINE_IRQ1:     set_irq_line(cpustate, INT1,   info->i);                break;
 2767          case CPUINFO_INT_INPUT_STATE + INPUT_LINE_IRQ2:     set_irq_line(cpustate, INT2,   info->i);                break;
 2768  
 2769          case CPUINFO_INT_PC:                                cpustate->pc.d = info->i;           break;
 2770          case CPUINFO_INT_REGISTER + T90_PC:                 cpustate->pc.w.l = info->i;                     break;
 2771          case CPUINFO_INT_SP:                                cpustate->sp.w.l = info->i;                     break;
 2772          case CPUINFO_INT_REGISTER + T90_SP:                 cpustate->sp.w.l = info->i;                     break;
 2773          case CPUINFO_INT_REGISTER + T90_A:                  cpustate->af.b.h = info->i;                     break;
 2774          case CPUINFO_INT_REGISTER + T90_B:                  cpustate->bc.b.h = info->i;                     break;
 2775          case CPUINFO_INT_REGISTER + T90_C:                  cpustate->bc.b.l = info->i;                     break;
 2776          case CPUINFO_INT_REGISTER + T90_D:                  cpustate->de.b.h = info->i;                     break;
 2777          case CPUINFO_INT_REGISTER + T90_E:                  cpustate->de.b.l = info->i;                     break;
 2778          case CPUINFO_INT_REGISTER + T90_H:                  cpustate->hl.b.h = info->i;                     break;
 2779          case CPUINFO_INT_REGISTER + T90_L:                  cpustate->hl.b.l = info->i;                     break;
 2780          case CPUINFO_INT_REGISTER + T90_AF:                 cpustate->af.w.l = info->i;                     break;
 2781          case CPUINFO_INT_REGISTER + T90_BC:                 cpustate->bc.w.l = info->i;                     break;
 2782          case CPUINFO_INT_REGISTER + T90_DE:                 cpustate->de.w.l = info->i;                     break;
 2783          case CPUINFO_INT_REGISTER + T90_HL:                 cpustate->hl.w.l = info->i;                     break;
 2784          case CPUINFO_INT_REGISTER + T90_IX:                 cpustate->ix.w.l = info->i;                     break;
 2785          case CPUINFO_INT_REGISTER + T90_IY:                 cpustate->iy.w.l = info->i;                     break;
 2786      }
 2787  }
 2788  
 2789  CPU_GET_INFO( tmp90840 )
 2790  {
 2791      t90_Regs *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
 2792  
 2793      switch (state)
 2794      {
 2795          /* --- the following bits of info are returned as 64-bit signed integers --- */
 2796  
 2797          case CPUINFO_INT_CONTEXT_SIZE:                              info->i = sizeof(t90_Regs);         break;
 2798          case CPUINFO_INT_INPUT_LINES:                               info->i = 1;                    break;
 2799          case CPUINFO_INT_DEFAULT_IRQ_VECTOR:                        info->i = 0xff;                 break;
 2800          case CPUINFO_INT_ENDIANNESS:                                info->i = ENDIANNESS_LITTLE;            break;
 2801          case CPUINFO_INT_CLOCK_MULTIPLIER:                          info->i = 1;                    break;
 2802          case CPUINFO_INT_CLOCK_DIVIDER:                             info->i = 1;                    break;
 2803          case CPUINFO_INT_MIN_INSTRUCTION_BYTES:                     info->i = 1;                    break;
 2804          case CPUINFO_INT_MAX_INSTRUCTION_BYTES:                     info->i = 6;                    break;
 2805          case CPUINFO_INT_MIN_CYCLES:                                info->i = 2;                    break;
 2806          case CPUINFO_INT_MAX_CYCLES:                                info->i = 26;                   break;
 2807  
 2808          case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:        info->i = 8;                    break;
 2809          case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM:        info->i = 20;                   break;
 2810          case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM:        info->i = 0;                    break;
 2811  
 2812          case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:       info->i = 0;                    break;
 2813          case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:       info->i = 0;                    break;
 2814          case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:       info->i = 0;                    break;
 2815  
 2816          case CPUINFO_INT_DATABUS_WIDTH + AS_IO:         info->i = 8;                    break;
 2817          case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:         info->i = 16;                   break;
 2818          case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO:         info->i = 0;                    break;
 2819  
 2820          case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI:              info->i = cpustate->irq_state & (1 << INTNMI);  break;
 2821          case CPUINFO_INT_INPUT_STATE + INPUT_LINE_IRQ0:             info->i = cpustate->irq_state & (1 << INT0);        break;
 2822          case CPUINFO_INT_INPUT_STATE + INPUT_LINE_IRQ1:             info->i = cpustate->irq_state & (1 << INT1);        break;
 2823          case CPUINFO_INT_INPUT_STATE + INPUT_LINE_IRQ2:             info->i = cpustate->irq_state & (1 << INT2);        break;
 2824  
 2825          case CPUINFO_INT_PREVIOUSPC:                                info->i = cpustate->prvpc.w.l;      break;
 2826          case CPUINFO_INT_PC:                                        info->i = cpustate->pc.d;               break;
 2827          case CPUINFO_INT_REGISTER + T90_PC:                         info->i = cpustate->pc.w.l;         break;
 2828          case CPUINFO_INT_SP:                                        info->i = cpustate->sp.d;               break;
 2829          case CPUINFO_INT_REGISTER + T90_SP:                         info->i = cpustate->sp.w.l;         break;
 2830          case CPUINFO_INT_REGISTER + T90_A:                          info->i = cpustate->af.b.h;         break;
 2831          case CPUINFO_INT_REGISTER + T90_B:                          info->i = cpustate->bc.b.h;         break;
 2832          case CPUINFO_INT_REGISTER + T90_C:                          info->i = cpustate->bc.b.l;         break;
 2833          case CPUINFO_INT_REGISTER + T90_D:                          info->i = cpustate->de.b.h;         break;
 2834          case CPUINFO_INT_REGISTER + T90_E:                          info->i = cpustate->de.b.l;         break;
 2835          case CPUINFO_INT_REGISTER + T90_H:                          info->i = cpustate->hl.b.h;         break;
 2836          case CPUINFO_INT_REGISTER + T90_L:                          info->i = cpustate->hl.b.l;         break;
 2837          case CPUINFO_INT_REGISTER + T90_AF:                         info->i = cpustate->af.w.l;         break;
 2838          case CPUINFO_INT_REGISTER + T90_BC:                         info->i = cpustate->bc.w.l;         break;
 2839          case CPUINFO_INT_REGISTER + T90_DE:                         info->i = cpustate->de.w.l;         break;
 2840          case CPUINFO_INT_REGISTER + T90_HL:                         info->i = cpustate->hl.w.l;         break;
 2841          case CPUINFO_INT_REGISTER + T90_IX:                         info->i = cpustate->ix.w.l;         break;
 2842          case CPUINFO_INT_REGISTER + T90_IY:                         info->i = cpustate->iy.w.l;         break;
 2843  
 2844          /* --- the following bits of info are returned as pointers to data or functions --- */
 2845  
 2846          case CPUINFO_FCT_SET_INFO:                                  info->setinfo = CPU_SET_INFO_NAME(t90);     break;
 2847          case CPUINFO_FCT_INIT:                                      info->init = CPU_INIT_NAME(t90);                break;
 2848          case CPUINFO_FCT_RESET:                                     info->reset = CPU_RESET_NAME(t90);          break;
 2849          case CPUINFO_FCT_EXIT:                                      info->exit = CPU_EXIT_NAME(t90);                break;
 2850          case CPUINFO_FCT_EXECUTE:                                   info->execute = CPU_EXECUTE_NAME(t90);      break;
 2851          case CPUINFO_FCT_BURN:                                      info->burn = CPU_BURN_NAME(t90);                break;
 2852          case CPUINFO_FCT_DISASSEMBLE:                               info->disassemble = CPU_DISASSEMBLE_NAME(t90);      break;
 2853          case CPUINFO_PTR_INSTRUCTION_COUNTER:                       info->icount = &cpustate->icount;           break;
 2854          case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(tmp90840_mem); break;
 2855  
 2856          /* --- the following bits of info are returned as NULL-terminated strings --- */
 2857  
 2858          case CPUINFO_STR_NAME:              strcpy(info->s, "TMP90840");            break;
 2859          case CPUINFO_STR_FAMILY:        strcpy(info->s, "Toshiba TLCS-90"); break;
 2860          case CPUINFO_STR_VERSION:       strcpy(info->s, "1.0");             break;
 2861          case CPUINFO_STR_SOURCE_FILE:           strcpy(info->s, __FILE__);          break;
 2862          case CPUINFO_STR_CREDITS:       strcpy(info->s, "Luca Elia");           break;
 2863  
 2864          case CPUINFO_STR_FLAGS:
 2865              sprintf(info->s, "%c%c%c%c%c%c%c%c",
 2866                  F & 0x80 ? 'S':'.',
 2867                  F & 0x40 ? 'Z':'.',
 2868                  F & 0x20 ? 'I':'.',
 2869                  F & 0x10 ? 'H':'.',
 2870                  F & 0x08 ? 'X':'.',
 2871                  F & 0x04 ? 'P':'.',
 2872                  F & 0x02 ? 'N':'.',
 2873                  F & 0x01 ? 'C':'.');
 2874              break;
 2875  
 2876          case CPUINFO_STR_REGISTER + T90_PC:     sprintf(info->s, "PC:%04X", cpustate->pc.w.l);  break;
 2877          case CPUINFO_STR_REGISTER + T90_SP:     sprintf(info->s, "SP:%04X", cpustate->sp.w.l);  break;
 2878          case CPUINFO_STR_REGISTER + T90_A:      sprintf(info->s, "~A:%02X", cpustate->af.b.h);  break;
 2879          case CPUINFO_STR_REGISTER + T90_B:      sprintf(info->s, "~B:%02X", cpustate->bc.b.h);  break;
 2880          case CPUINFO_STR_REGISTER + T90_C:      sprintf(info->s, "~C:%02X", cpustate->bc.b.l);  break;
 2881          case CPUINFO_STR_REGISTER + T90_D:      sprintf(info->s, "~D:%02X", cpustate->de.b.h);  break;
 2882          case CPUINFO_STR_REGISTER + T90_E:      sprintf(info->s, "~E:%02X", cpustate->de.b.l);  break;
 2883          case CPUINFO_STR_REGISTER + T90_H:      sprintf(info->s, "~H:%02X", cpustate->hl.b.h);  break;
 2884          case CPUINFO_STR_REGISTER + T90_L:      sprintf(info->s, "~L:%02X", cpustate->hl.b.l);  break;
 2885          case CPUINFO_STR_REGISTER + T90_AF:     sprintf(info->s, "AF:%04X", cpustate->af.w.l);  break;
 2886          case CPUINFO_STR_REGISTER + T90_BC:     sprintf(info->s, "BC:%04X", cpustate->bc.w.l);  break;
 2887          case CPUINFO_STR_REGISTER + T90_DE:     sprintf(info->s, "DE:%04X", cpustate->de.w.l);  break;
 2888          case CPUINFO_STR_REGISTER + T90_HL:     sprintf(info->s, "HL:%04X", cpustate->hl.w.l);  break;
 2889          case CPUINFO_STR_REGISTER + T90_IX:     sprintf(info->s, "IX:%04X", cpustate->ix.w.l);  break;
 2890          case CPUINFO_STR_REGISTER + T90_IY:     sprintf(info->s, "IY:%04X", cpustate->iy.w.l);  break;
 2891      }
 2892  }
 2893  
 2894  CPU_GET_INFO( tmp90841 )
 2895  {
 2896      switch (state)
 2897      {
 2898          /* --- the following bits of info are returned as 64-bit signed integers --- */
 2899  
 2900          case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(tmp90841_mem); return;
 2901  
 2902          /* --- the following bits of info are returned as NULL-terminated strings --- */
 2903  
 2904          case CPUINFO_STR_NAME:              strcpy(info->s, "TMP90841");            return;
 2905      }
 2906  
 2907      CPU_GET_INFO_CALL(tmp90840);
 2908  }
 2909  
 2910  CPU_GET_INFO( tmp91640 )
 2911  {
 2912      switch (state)
 2913      {
 2914          /* --- the following bits of info are returned as 64-bit signed integers --- */
 2915  
 2916          case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(tmp91640_mem); return;
 2917  
 2918          /* --- the following bits of info are returned as NULL-terminated strings --- */
 2919  
 2920          case CPUINFO_STR_NAME:              strcpy(info->s, "TMP91640");            return;
 2921      }
 2922  
 2923      CPU_GET_INFO_CALL(tmp90840);
 2924  }
 2925  
 2926  CPU_GET_INFO( tmp91641 )
 2927  {
 2928      switch (state)
 2929      {
 2930          /* --- the following bits of info are returned as 64-bit signed integers --- */
 2931  
 2932          case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(tmp91641_mem); return;
 2933  
 2934          /* --- the following bits of info are returned as NULL-terminated strings --- */
 2935  
 2936          case CPUINFO_STR_NAME:              strcpy(info->s, "TMP91641");            return;
 2937      }
 2938  
 2939      CPU_GET_INFO_CALL(tmp90840);
 2940  }
 2941  
 2942  DEFINE_LEGACY_CPU_DEVICE(TMP90840, tmp90840);
 2943  DEFINE_LEGACY_CPU_DEVICE(TMP90841, tmp90841);
 2944  DEFINE_LEGACY_CPU_DEVICE(TMP91640, tmp91640);
 2945  DEFINE_LEGACY_CPU_DEVICE(TMP91641, tmp91641);