Viewing File: <root>/src/emu/cpu/v60/v60.c

    1  // V60.C
    2  // Undiscover the beast!
    3  // Main hacking and coding by Farfetch'd
    4  // Portability fixes by Richter Belmont
    5  
    6  #include "emu.h"
    7  #include "debugger.h"
    8  #include "v60.h"
    9  
   10  // memory accessors
   11  #if defined(LSB_FIRST) && !defined(ALIGN_INTS)
   12  #define OpRead8(s, a)   ((s)->direct->read_decrypted_byte(a))
   13  #define OpRead16(s, a)  ((s)->direct->read_decrypted_word(a))
   14  #define OpRead32(s, a)  ((s)->direct->read_decrypted_dword(a))
   15  #else
   16  #define OpRead8(s, a)   ((s)->direct->read_decrypted_byte((a), (s)->fetch_xor))
   17  #define OpRead16(s, a)  (((s)->direct->read_decrypted_byte(((a)+0), (s)->fetch_xor) << 0) | \
   18                              ((s)->direct->read_decrypted_byte(((a)+1), (s)->fetch_xor) << 8))
   19  #define OpRead32(s, a)  (((s)->direct->read_decrypted_byte(((a)+0), (s)->fetch_xor) << 0) | \
   20                              ((s)->direct->read_decrypted_byte(((a)+1), (s)->fetch_xor) << 8) | \
   21                              ((s)->direct->read_decrypted_byte(((a)+2), (s)->fetch_xor) << 16) | \
   22                              ((s)->direct->read_decrypted_byte(((a)+3), (s)->fetch_xor) << 24))
   23  #endif
   24  
   25  
   26  // macros stolen from MAME for flags calc
   27  // note that these types are in x86 naming:
   28  // byte = 8 bit, word = 16 bit, long = 32 bit
   29  
   30  // parameter x = result, y = source 1, z = source 2
   31  
   32  #define SetOFL_Add(x, y,z)  (cpustate->_OV = (((x) ^ (y)) & ((x) ^ (z)) & 0x80000000) ? 1: 0)
   33  #define SetOFW_Add(x, y,z)  (cpustate->_OV = (((x) ^ (y)) & ((x) ^ (z)) & 0x8000) ? 1 : 0)
   34  #define SetOFB_Add(x, y,z)  (cpustate->_OV = (((x) ^ (y)) & ((x) ^ (z)) & 0x80) ? 1 : 0)
   35  
   36  #define SetOFL_Sub(x, y,z)  (cpustate->_OV = (((z) ^ (y)) & ((z) ^ (x)) & 0x80000000) ? 1 : 0)
   37  #define SetOFW_Sub(x, y,z)  (cpustate->_OV = (((z) ^ (y)) & ((z) ^ (x)) & 0x8000) ? 1 : 0)
   38  #define SetOFB_Sub(x, y,z)  (cpustate->_OV = (((z) ^ (y)) & ((z) ^ (x)) & 0x80) ? 1 : 0)
   39  
   40  #define SetCFB(x)           {cpustate->_CY = ((x) & 0x100) ? 1 : 0; }
   41  #define SetCFW(x)           {cpustate->_CY = ((x) & 0x10000) ? 1 : 0; }
   42  #define SetCFL(x)           {cpustate->_CY = ((x) & (((UINT64)1) << 32)) ? 1 : 0; }
   43  
   44  #define SetSF(x)            (cpustate->_S = (x))
   45  #define SetZF(x)            (cpustate->_Z = (x))
   46  
   47  #define SetSZPF_Byte(x)     {cpustate->_Z = ((UINT8)(x) == 0);  cpustate->_S = ((x)&0x80) ? 1 : 0; }
   48  #define SetSZPF_Word(x)     {cpustate->_Z = ((UINT16)(x) == 0);  cpustate->_S = ((x)&0x8000) ? 1 : 0; }
   49  #define SetSZPF_Long(x)     {cpustate->_Z = ((UINT32)(x) == 0);  cpustate->_S = ((x)&0x80000000) ? 1 : 0; }
   50  
   51  #define ORB(dst, src)       { (dst) |= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Byte(dst); }
   52  #define ORW(dst, src)       { (dst) |= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Word(dst); }
   53  #define ORL(dst, src)       { (dst) |= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Long(dst); }
   54  
   55  #define ANDB(dst, src)      { (dst) &= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Byte(dst); }
   56  #define ANDW(dst, src)      { (dst) &= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Word(dst); }
   57  #define ANDL(dst, src)      { (dst) &= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Long(dst); }
   58  
   59  #define XORB(dst, src)      { (dst) ^= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Byte(dst); }
   60  #define XORW(dst, src)      { (dst) ^= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Word(dst); }
   61  #define XORL(dst, src)      { (dst) ^= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Long(dst); }
   62  
   63  #define SUBB(dst, src)      { unsigned res = (dst) - (src); SetCFB(res); SetOFB_Sub(res, src, dst); SetSZPF_Byte(res); dst = (UINT8)res; }
   64  #define SUBW(dst, src)      { unsigned res = (dst) - (src); SetCFW(res); SetOFW_Sub(res, src, dst); SetSZPF_Word(res); dst = (UINT16)res; }
   65  #define SUBL(dst, src)      { UINT64 res = (UINT64)(dst) - (INT64)(src); SetCFL(res); SetOFL_Sub(res, src, dst); SetSZPF_Long(res); dst = (UINT32)res; }
   66  
   67  #define ADDB(dst, src)      { unsigned res = (dst) + (src); SetCFB(res); SetOFB_Add(res, src, dst); SetSZPF_Byte(res); dst = (UINT8)res; }
   68  #define ADDW(dst, src)      { unsigned res = (dst) + (src); SetCFW(res); SetOFW_Add(res, src, dst); SetSZPF_Word(res); dst = (UINT16)res; }
   69  #define ADDL(dst, src)      { UINT64 res = (UINT64)(dst) + (UINT64)(src); SetCFL(res); SetOFL_Add(res, src, dst); SetSZPF_Long(res); dst = (UINT32)res; }
   70  
   71  #define SETREG8(a, b)       (a) = ((a) & ~0xff) | ((b) & 0xff)
   72  #define SETREG16(a, b)      (a) = ((a) & ~0xffff) | ((b) & 0xffff)
   73  
   74  struct v60_flags
   75  {
   76      UINT8 CY;
   77      UINT8 OV;
   78      UINT8 S;
   79      UINT8 Z;
   80  };
   81  
   82  // v60 Register Inside (Hm... It's not a pentium inside :-))) )
   83  struct v60_state
   84  {
   85      offs_t              fetch_xor;
   86      offs_t              start_pc;
   87      UINT32              reg[68];
   88      v60_flags           flags;
   89      UINT8               irq_line;
   90      UINT8               nmi_line;
   91      device_irq_acknowledge_callback irq_cb;
   92      legacy_cpu_device *     device;
   93      address_space *program;
   94      direct_read_data *  direct;
   95      address_space *io;
   96      UINT32              PPC;
   97      int                 icount;
   98      int                 stall_io;
   99  
  100      UINT32              op1, op2;
  101      UINT8               flag1, flag2;
  102      UINT8               instflags;
  103      UINT32              lenop1, lenop2;
  104      UINT8               subop;
  105      UINT32              bamoffset1, bamoffset2;
  106  
  107      // Output variables for ReadAMAddress(cpustate)
  108      UINT8               amflag;
  109      UINT32              amout;
  110      UINT32              bamoffset;
  111  
  112      // Appo temp var
  113      UINT32              amlength1, amlength2;
  114  
  115      // Global vars used by AM functions
  116      UINT32              modadd;
  117      UINT8               modm;
  118      UINT8               modval;
  119      UINT8               modval2;
  120      UINT8               modwritevalb;
  121      UINT16              modwritevalh;
  122      UINT32              modwritevalw;
  123      UINT8               moddim;
  124  };
  125  
  126  INLINE v60_state *get_safe_token(device_t *device)
  127  {
  128      assert(device != NULL);
  129      assert(device->type() == V60 ||
  130              device->type() == V70);
  131      return (v60_state *)downcast<legacy_cpu_device *>(device)->token();
  132  }
  133  
  134  /*
  135   * Prevent warnings on NetBSD.  All identifiers beginning with an underscore
  136   * followed by an uppercase letter are reserved by the C standard (ISO / IEC
  137   * 9899:1999, 7.1.3) to be used by the implementation.  It'd be best to rename
  138   * all such instances, but this is less intrusive and error-prone.
  139   */
  140  #undef _S
  141  
  142  #define _CY     flags.CY
  143  #define _OV     flags.OV
  144  #define _S      flags.S
  145  #define _Z      flags.Z
  146  
  147  
  148  // Defines of all v60 register...
  149  #define R0      reg[0]
  150  #define R1      reg[1]
  151  #define R2      reg[2]
  152  #define R3      reg[3]
  153  #define R4      reg[4]
  154  #define R5      reg[5]
  155  #define R6      reg[6]
  156  #define R7      reg[7]
  157  #define R8      reg[8]
  158  #define R9      reg[9]
  159  #define R10     reg[10]
  160  #define R11     reg[11]
  161  #define R12     reg[12]
  162  #define R13     reg[13]
  163  #define R14     reg[14]
  164  #define R15     reg[15]
  165  #define R16     reg[16]
  166  #define R17     reg[17]
  167  #define R18     reg[18]
  168  #define R19     reg[19]
  169  #define R20     reg[20]
  170  #define R21     reg[21]
  171  #define R22     reg[22]
  172  #define R23     reg[23]
  173  #define R24     reg[24]
  174  #define R25     reg[25]
  175  #define R26     reg[26]
  176  #define R27     reg[27]
  177  #define R28     reg[28]
  178  #define AP      reg[29]
  179  #define FP      reg[30]
  180  #define SP      reg[31]
  181  
  182  #define PC      reg[32]
  183  #define PSW     reg[33]
  184  
  185  // Privileged registers
  186  #define ISP     reg[36]
  187  #define L0SP    reg[37]
  188  #define L1SP    reg[38]
  189  #define L2SP    reg[39]
  190  #define L3SP    reg[40]
  191  #define SBR     reg[41]
  192  #define TR      reg[42]
  193  #define SYCW    reg[43]
  194  #define TKCW    reg[44]
  195  #define PIR     reg[45]
  196  //10-14 reserved
  197  #define PSW2    reg[51]
  198  #define ATBR0   reg[52]
  199  #define ATLR0   reg[53]
  200  #define ATBR1   reg[54]
  201  #define ATLR1   reg[55]
  202  #define ATBR2   reg[56]
  203  #define ATLR2   reg[57]
  204  #define ATBR3   reg[58]
  205  #define ATLR3   reg[59]
  206  #define TRMODE  reg[60]
  207  #define ADTR0   reg[61]
  208  #define ADTR1   reg[62]
  209  #define ADTMR0  reg[63]
  210  #define ADTMR1  reg[64]
  211  //29-31 reserved
  212  
  213  // Defines...
  214  #define NORMALIZEFLAGS(cs) \
  215  { \
  216      (cs)->_S    = (cs)->_S  ? 1 : 0; \
  217      (cs)->_OV   = (cs)->_OV ? 1 : 0; \
  218      (cs)->_Z    = (cs)->_Z  ? 1 : 0; \
  219      (cs)->_CY   = (cs)->_CY ? 1 : 0; \
  220  }
  221  
  222  static void v60_try_irq(v60_state *cpustate);
  223  
  224  
  225  INLINE void v60SaveStack(v60_state *cpustate)
  226  {
  227      if (cpustate->PSW & 0x10000000)
  228          cpustate->ISP = cpustate->SP;
  229      else
  230          cpustate->reg[37 + ((cpustate->PSW >> 24) & 3)] = cpustate->SP;
  231  }
  232  
  233  INLINE void v60ReloadStack(v60_state *cpustate)
  234  {
  235      if (cpustate->PSW & 0x10000000)
  236          cpustate->SP = cpustate->ISP;
  237      else
  238          cpustate->SP = cpustate->reg[37 + ((cpustate->PSW >> 24) & 3)];
  239  }
  240  
  241  INLINE UINT32 v60ReadPSW(v60_state *cpustate)
  242  {
  243      cpustate->PSW &= 0xfffffff0;
  244      cpustate->PSW |= (cpustate->_Z?1:0) | (cpustate->_S?2:0) | (cpustate->_OV?4:0) | (cpustate->_CY?8:0);
  245      return cpustate->PSW;
  246  }
  247  
  248  INLINE void v60WritePSW(v60_state *cpustate, UINT32 newval)
  249  {
  250      /* determine if we need to save / restore the stacks */
  251      int updateStack = 0;
  252  
  253      /* if the interrupt state is changing, we definitely need to update */
  254      if ((newval ^ cpustate->PSW) & 0x10000000)
  255          updateStack = 1;
  256  
  257      /* if we are not in interrupt mode and the level is changing, we also must update */
  258      else if (!(cpustate->PSW & 0x10000000) && ((newval ^ cpustate->PSW) & 0x03000000))
  259          updateStack = 1;
  260  
  261      /* save the previous stack value */
  262      if (updateStack)
  263          v60SaveStack(cpustate);
  264  
  265      /* set the new value and update the flags */
  266      cpustate->PSW = newval;
  267      cpustate->_Z =  (UINT8)(cpustate->PSW & 1);
  268      cpustate->_S =  (UINT8)(cpustate->PSW & 2);
  269      cpustate->_OV = (UINT8)(cpustate->PSW & 4);
  270      cpustate->_CY = (UINT8)(cpustate->PSW & 8);
  271  
  272      /* fetch the new stack value */
  273      if (updateStack)
  274          v60ReloadStack(cpustate);
  275  }
  276  
  277  
  278  INLINE UINT32 v60_update_psw_for_exception(v60_state *cpustate, int is_interrupt, int target_level)
  279  {
  280      UINT32 oldPSW = v60ReadPSW(cpustate);
  281      UINT32 newPSW = oldPSW;
  282  
  283      // Change to interrupt context
  284      newPSW &= ~(3 << 24);  // cpustate->PSW.EL = 0
  285      newPSW |= target_level << 24; // set target level
  286      newPSW &= ~(1 << 18);  // cpustate->PSW.IE = 0
  287      newPSW &= ~(1 << 16);  // cpustate->PSW.TE = 0
  288      newPSW &= ~(1 << 27);  // cpustate->PSW.TP = 0
  289      newPSW &= ~(1 << 17);  // cpustate->PSW.AE = 0
  290      newPSW &= ~(1 << 29);  // cpustate->PSW.EM = 0
  291      if (is_interrupt)
  292          newPSW |=  (1 << 28);// cpustate->PSW.IS = 1
  293      newPSW |=  (1 << 31);  // cpustate->PSW.ASA = 1
  294      v60WritePSW(cpustate, newPSW);
  295  
  296      return oldPSW;
  297  }
  298  
  299  
  300  #define GETINTVECT(cs, nint)                    (cs)->program->read_dword(((cs)->SBR & ~0xfff) + (nint) * 4)
  301  #define EXCEPTION_CODE_AND_SIZE(code, size) (((code) << 16) | (size))
  302  
  303  
  304  // Addressing mode decoding functions
  305  #include "am.c"
  306  
  307  // Opcode functions
  308  #include "op12.c"
  309  #include "op2.c"
  310  #include "op3.c"
  311  #include "op4.c"
  312  #include "op5.c"
  313  #include "op6.c"
  314  #include "op7a.c"
  315  
  316  static UINT32 opUNHANDLED(v60_state *cpustate)
  317  {
  318      fatalerror("Unhandled OpCode found : %02x at %08x\n", OpRead16(cpustate, cpustate->PC), cpustate->PC);
  319      return 0; /* never reached, fatalerror won't return */
  320  }
  321  
  322  // Opcode jump table
  323  #include "optable.c"
  324  
  325  static void base_init(legacy_cpu_device *device, device_irq_acknowledge_callback irqcallback)
  326  {
  327      v60_state *cpustate = get_safe_token(device);
  328  
  329      cpustate->stall_io = 0;
  330      cpustate->irq_cb = irqcallback;
  331      cpustate->device = device;
  332      cpustate->irq_line = CLEAR_LINE;
  333      cpustate->nmi_line = CLEAR_LINE;
  334  
  335      device->save_item(NAME(cpustate->reg));
  336      device->save_item(NAME(cpustate->irq_line));
  337      device->save_item(NAME(cpustate->nmi_line));
  338      device->save_item(NAME(cpustate->PPC));
  339      device->save_item(NAME(cpustate->_CY));
  340      device->save_item(NAME(cpustate->_OV));
  341      device->save_item(NAME(cpustate->_S));
  342      device->save_item(NAME(cpustate->_Z));
  343  }
  344  
  345  static CPU_INIT( v60 )
  346  {
  347      v60_state *cpustate = get_safe_token(device);
  348  
  349      base_init(device, irqcallback);
  350      // Set cpustate->PIR (Processor ID) for NEC cpustate-> LSB is reserved to NEC,
  351      // so I don't know what it contains.
  352      cpustate->PIR = 0x00006000;
  353      cpustate->fetch_xor = BYTE_XOR_LE(0);
  354      cpustate->start_pc = 0xfffff0;
  355      cpustate->device = device;
  356      cpustate->program = &device->space(AS_PROGRAM);
  357      cpustate->direct = &cpustate->program->direct();
  358      cpustate->io = &device->space(AS_IO);
  359  }
  360  
  361  static CPU_INIT( v70 )
  362  {
  363      v60_state *cpustate = get_safe_token(device);
  364  
  365      base_init(device, irqcallback);
  366      // Set cpustate->PIR (Processor ID) for NEC v70. LSB is reserved to NEC,
  367      // so I don't know what it contains.
  368      cpustate->PIR = 0x00007000;
  369      cpustate->fetch_xor = BYTE4_XOR_LE(0);
  370      cpustate->start_pc = 0xfffffff0;
  371      cpustate->device = device;
  372      cpustate->program = &device->space(AS_PROGRAM);
  373      cpustate->direct = &cpustate->program->direct();
  374      cpustate->io = &device->space(AS_IO);
  375  }
  376  
  377  static CPU_RESET( v60 )
  378  {
  379      v60_state *cpustate = get_safe_token(device);
  380  
  381      cpustate->PSW   = 0x10000000;
  382      cpustate->PC    = cpustate->start_pc;
  383      cpustate->SBR   = 0x00000000;
  384      cpustate->SYCW  = 0x00000070;
  385      cpustate->TKCW  = 0x0000e000;
  386      cpustate->PSW2  = 0x0000f002;
  387  
  388      cpustate->_CY   = 0;
  389      cpustate->_OV   = 0;
  390      cpustate->_S    = 0;
  391      cpustate->_Z    = 0;
  392  }
  393  
  394  static CPU_EXIT( v60 )
  395  {
  396  }
  397  
  398  void v60_stall(device_t *device)
  399  {
  400      v60_state *cpustate = get_safe_token(device);
  401      cpustate->stall_io = 1;
  402  }
  403  
  404  static void v60_do_irq(v60_state *cpustate, int vector)
  405  {
  406      UINT32 oldPSW = v60_update_psw_for_exception(cpustate, 1, 0);
  407  
  408      // Push cpustate->PC and cpustate->PSW onto the stack
  409      cpustate->SP-=4;
  410      cpustate->program->write_dword_unaligned(cpustate->SP, oldPSW);
  411      cpustate->SP-=4;
  412      cpustate->program->write_dword_unaligned(cpustate->SP, cpustate->PC);
  413  
  414      // Jump to vector for user interrupt
  415      cpustate->PC = GETINTVECT(cpustate, vector);
  416  }
  417  
  418  static void v60_try_irq(v60_state *cpustate)
  419  {
  420      if(cpustate->irq_line == CLEAR_LINE)
  421          return;
  422      if((cpustate->PSW & (1 << 18)) != 0) {
  423          int vector;
  424          if(cpustate->irq_line != ASSERT_LINE)
  425              cpustate->irq_line = CLEAR_LINE;
  426  
  427          vector = cpustate->irq_cb(cpustate->device, 0);
  428  
  429          v60_do_irq(cpustate, vector + 0x40);
  430      }
  431  }
  432  
  433  static void set_irq_line(v60_state *cpustate, int irqline, int state)
  434  {
  435      if(irqline == INPUT_LINE_NMI) {
  436          switch(state) {
  437          case ASSERT_LINE:
  438              if(cpustate->nmi_line == CLEAR_LINE) {
  439                  cpustate->nmi_line = ASSERT_LINE;
  440                  v60_do_irq(cpustate, 2);
  441              }
  442              break;
  443          case CLEAR_LINE:
  444              cpustate->nmi_line = CLEAR_LINE;
  445              break;
  446          }
  447      } else {
  448          cpustate->irq_line = state;
  449          v60_try_irq(cpustate);
  450      }
  451  }
  452  
  453  // Actual cycles / instruction is unknown
  454  
  455  static CPU_EXECUTE( v60 )
  456  {
  457      v60_state *cpustate = get_safe_token(device);
  458  
  459      if (cpustate->irq_line != CLEAR_LINE)
  460          v60_try_irq(cpustate);
  461  
  462      while (cpustate->icount > 0)
  463      {
  464          UINT32 inc;
  465          cpustate->PPC = cpustate->PC;
  466          debugger_instruction_hook(device, cpustate->PC);
  467          cpustate->icount -= 8;  /* fix me -- this is just an average */
  468          inc = OpCodeTable[OpRead8(cpustate, cpustate->PC)](cpustate);
  469          cpustate->PC += inc;
  470          if (cpustate->irq_line != CLEAR_LINE)
  471              v60_try_irq(cpustate);
  472      }
  473  }
  474  
  475  
  476  CPU_DISASSEMBLE( v60 );
  477  CPU_DISASSEMBLE( v70 );
  478  
  479  
  480  /**************************************************************************
  481   * Generic set_info
  482   **************************************************************************/
  483  
  484  static CPU_SET_INFO( v60 )
  485  {
  486      v60_state *cpustate = get_safe_token(device);
  487  
  488      switch (state)
  489      {
  490          /* --- the following bits of info are set as 64-bit signed integers --- */
  491          case CPUINFO_INT_INPUT_STATE + 0:               set_irq_line(cpustate, 0, info->i);             break;
  492          case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI:  set_irq_line(cpustate, INPUT_LINE_NMI, info->i);break;
  493  
  494          case CPUINFO_INT_PC:                            cpustate->PC = info->i;                         break;
  495          case CPUINFO_INT_SP:                            cpustate->SP = info->i;                         break;
  496  
  497          case CPUINFO_INT_REGISTER + V60_R0:             cpustate->R0 = info->i;                         break;
  498          case CPUINFO_INT_REGISTER + V60_R1:             cpustate->R1 = info->i;                         break;
  499          case CPUINFO_INT_REGISTER + V60_R2:             cpustate->R2 = info->i;                         break;
  500          case CPUINFO_INT_REGISTER + V60_R3:             cpustate->R3 = info->i;                         break;
  501          case CPUINFO_INT_REGISTER + V60_R4:             cpustate->R4 = info->i;                         break;
  502          case CPUINFO_INT_REGISTER + V60_R5:             cpustate->R5 = info->i;                         break;
  503          case CPUINFO_INT_REGISTER + V60_R6:             cpustate->R6 = info->i;                         break;
  504          case CPUINFO_INT_REGISTER + V60_R7:             cpustate->R7 = info->i;                         break;
  505          case CPUINFO_INT_REGISTER + V60_R8:             cpustate->R8 = info->i;                         break;
  506          case CPUINFO_INT_REGISTER + V60_R9:             cpustate->R9 = info->i;                         break;
  507          case CPUINFO_INT_REGISTER + V60_R10:            cpustate->R10 = info->i;                        break;
  508          case CPUINFO_INT_REGISTER + V60_R11:            cpustate->R11 = info->i;                        break;
  509          case CPUINFO_INT_REGISTER + V60_R12:            cpustate->R12 = info->i;                        break;
  510          case CPUINFO_INT_REGISTER + V60_R13:            cpustate->R13 = info->i;                        break;
  511          case CPUINFO_INT_REGISTER + V60_R14:            cpustate->R14 = info->i;                        break;
  512          case CPUINFO_INT_REGISTER + V60_R15:            cpustate->R15 = info->i;                        break;
  513          case CPUINFO_INT_REGISTER + V60_R16:            cpustate->R16 = info->i;                        break;
  514          case CPUINFO_INT_REGISTER + V60_R17:            cpustate->R17 = info->i;                        break;
  515          case CPUINFO_INT_REGISTER + V60_R18:            cpustate->R18 = info->i;                        break;
  516          case CPUINFO_INT_REGISTER + V60_R19:            cpustate->R19 = info->i;                        break;
  517          case CPUINFO_INT_REGISTER + V60_R20:            cpustate->R20 = info->i;                        break;
  518          case CPUINFO_INT_REGISTER + V60_R21:            cpustate->R21 = info->i;                        break;
  519          case CPUINFO_INT_REGISTER + V60_R22:            cpustate->R22 = info->i;                        break;
  520          case CPUINFO_INT_REGISTER + V60_R23:            cpustate->R23 = info->i;                        break;
  521          case CPUINFO_INT_REGISTER + V60_R24:            cpustate->R24 = info->i;                        break;
  522          case CPUINFO_INT_REGISTER + V60_R25:            cpustate->R25 = info->i;                        break;
  523          case CPUINFO_INT_REGISTER + V60_R26:            cpustate->R26 = info->i;                        break;
  524          case CPUINFO_INT_REGISTER + V60_R27:            cpustate->R27 = info->i;                        break;
  525          case CPUINFO_INT_REGISTER + V60_R28:            cpustate->R28 = info->i;                        break;
  526          case CPUINFO_INT_REGISTER + V60_AP:             cpustate->AP = info->i;                         break;
  527          case CPUINFO_INT_REGISTER + V60_FP:             cpustate->FP = info->i;                         break;
  528          case CPUINFO_INT_REGISTER + V60_SP:             cpustate->SP = info->i;                         break;
  529          case CPUINFO_INT_REGISTER + V60_PC:             cpustate->PC = info->i;                         break;
  530          case CPUINFO_INT_REGISTER + V60_PSW:            v60WritePSW(cpustate, info->i);                 break;
  531          case CPUINFO_INT_REGISTER + V60_ISP:            cpustate->ISP = info->i;                        break;
  532          case CPUINFO_INT_REGISTER + V60_L0SP:           cpustate->L0SP = info->i;                       break;
  533          case CPUINFO_INT_REGISTER + V60_L1SP:           cpustate->L1SP = info->i;                       break;
  534          case CPUINFO_INT_REGISTER + V60_L2SP:           cpustate->L2SP = info->i;                       break;
  535          case CPUINFO_INT_REGISTER + V60_L3SP:           cpustate->L3SP = info->i;                       break;
  536          case CPUINFO_INT_REGISTER + V60_SBR:            cpustate->SBR = info->i;                        break;
  537          case CPUINFO_INT_REGISTER + V60_TR:             cpustate->TR = info->i;                         break;
  538          case CPUINFO_INT_REGISTER + V60_SYCW:           cpustate->SYCW = info->i;                       break;
  539          case CPUINFO_INT_REGISTER + V60_TKCW:           cpustate->TKCW = info->i;                       break;
  540          case CPUINFO_INT_REGISTER + V60_PIR:            cpustate->PIR = info->i;                        break;
  541          case CPUINFO_INT_REGISTER + V60_PSW2:           cpustate->PSW2 = info->i;                       break;
  542          case CPUINFO_INT_REGISTER + V60_ATBR0:          cpustate->ATBR0 = info->i;                      break;
  543          case CPUINFO_INT_REGISTER + V60_ATLR0:          cpustate->ATLR0 = info->i;                      break;
  544          case CPUINFO_INT_REGISTER + V60_ATBR1:          cpustate->ATBR1 = info->i;                      break;
  545          case CPUINFO_INT_REGISTER + V60_ATLR1:          cpustate->ATLR1 = info->i;                      break;
  546          case CPUINFO_INT_REGISTER + V60_ATBR2:          cpustate->ATBR2 = info->i;                      break;
  547          case CPUINFO_INT_REGISTER + V60_ATLR2:          cpustate->ATLR2 = info->i;                      break;
  548          case CPUINFO_INT_REGISTER + V60_ATBR3:          cpustate->ATBR3 = info->i;                      break;
  549          case CPUINFO_INT_REGISTER + V60_ATLR3:          cpustate->ATLR3 = info->i;                      break;
  550          case CPUINFO_INT_REGISTER + V60_TRMODE:         cpustate->TRMODE = info->i;                     break;
  551          case CPUINFO_INT_REGISTER + V60_ADTR0:          cpustate->ADTR0 = info->i;                      break;
  552          case CPUINFO_INT_REGISTER + V60_ADTR1:          cpustate->ADTR1 = info->i;                      break;
  553          case CPUINFO_INT_REGISTER + V60_ADTMR0:         cpustate->ADTMR0 = info->i;                     break;
  554          case CPUINFO_INT_REGISTER + V60_ADTMR1:         cpustate->ADTMR1 = info->i;                     break;
  555      }
  556  }
  557  
  558  
  559  
  560  /**************************************************************************
  561   * Generic get_info
  562   **************************************************************************/
  563  
  564  CPU_GET_INFO( v60 )
  565  {
  566      v60_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
  567  
  568      switch (state)
  569      {
  570          /* --- the following bits of info are returned as 64-bit signed integers --- */
  571          case CPUINFO_INT_CONTEXT_SIZE:                  info->i = sizeof(v60_state);            break;
  572          case CPUINFO_INT_INPUT_LINES:                   info->i = 1;                            break;
  573          case CPUINFO_INT_DEFAULT_IRQ_VECTOR:            info->i = 0;                            break;
  574          case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;            break;
  575          case CPUINFO_INT_CLOCK_MULTIPLIER:              info->i = 1;                            break;
  576          case CPUINFO_INT_CLOCK_DIVIDER:                 info->i = 1;                            break;
  577          case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 1;                            break;
  578          case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 22;                           break;
  579          case CPUINFO_INT_MIN_CYCLES:                    info->i = 1;                            break;
  580          case CPUINFO_INT_MAX_CYCLES:                    info->i = 1;                            break;
  581  
  582          case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:    info->i = 16;                   break;
  583          case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24;                  break;
  584          case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0;                   break;
  585          case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:   info->i = 0;                    break;
  586          case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:   info->i = 0;                    break;
  587          case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:   info->i = 0;                    break;
  588          case CPUINFO_INT_DATABUS_WIDTH + AS_IO:     info->i = 16;                   break;
  589          case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:     info->i = 24;                   break;
  590          case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO:     info->i = 0;                    break;
  591  
  592          case CPUINFO_INT_INPUT_STATE + 0:               info->i = cpustate->irq_line;           break;
  593          case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI:  info->i = cpustate->nmi_line;           break;
  594  
  595          case CPUINFO_INT_PREVIOUSPC:                    info->i = cpustate->PPC;                break;
  596  
  597          case CPUINFO_INT_REGISTER + V60_R0:             info->i = cpustate->R0;                 break;
  598          case CPUINFO_INT_REGISTER + V60_R1:             info->i = cpustate->R1;                 break;
  599          case CPUINFO_INT_REGISTER + V60_R2:             info->i = cpustate->R2;                 break;
  600          case CPUINFO_INT_REGISTER + V60_R3:             info->i = cpustate->R3;                 break;
  601          case CPUINFO_INT_REGISTER + V60_R4:             info->i = cpustate->R4;                 break;
  602          case CPUINFO_INT_REGISTER + V60_R5:             info->i = cpustate->R5;                 break;
  603          case CPUINFO_INT_REGISTER + V60_R6:             info->i = cpustate->R6;                 break;
  604          case CPUINFO_INT_REGISTER + V60_R7:             info->i = cpustate->R7;                 break;
  605          case CPUINFO_INT_REGISTER + V60_R8:             info->i = cpustate->R8;                 break;
  606          case CPUINFO_INT_REGISTER + V60_R9:             info->i = cpustate->R9;                 break;
  607          case CPUINFO_INT_REGISTER + V60_R10:            info->i = cpustate->R10;                break;
  608          case CPUINFO_INT_REGISTER + V60_R11:            info->i = cpustate->R11;                break;
  609          case CPUINFO_INT_REGISTER + V60_R12:            info->i = cpustate->R12;                break;
  610          case CPUINFO_INT_REGISTER + V60_R13:            info->i = cpustate->R13;                break;
  611          case CPUINFO_INT_REGISTER + V60_R14:            info->i = cpustate->R14;                break;
  612          case CPUINFO_INT_REGISTER + V60_R15:            info->i = cpustate->R15;                break;
  613          case CPUINFO_INT_REGISTER + V60_R16:            info->i = cpustate->R16;                break;
  614          case CPUINFO_INT_REGISTER + V60_R17:            info->i = cpustate->R17;                break;
  615          case CPUINFO_INT_REGISTER + V60_R18:            info->i = cpustate->R18;                break;
  616          case CPUINFO_INT_REGISTER + V60_R19:            info->i = cpustate->R19;                break;
  617          case CPUINFO_INT_REGISTER + V60_R20:            info->i = cpustate->R20;                break;
  618          case CPUINFO_INT_REGISTER + V60_R21:            info->i = cpustate->R21;                break;
  619          case CPUINFO_INT_REGISTER + V60_R22:            info->i = cpustate->R22;                break;
  620          case CPUINFO_INT_REGISTER + V60_R23:            info->i = cpustate->R23;                break;
  621          case CPUINFO_INT_REGISTER + V60_R24:            info->i = cpustate->R24;                break;
  622          case CPUINFO_INT_REGISTER + V60_R25:            info->i = cpustate->R25;                break;
  623          case CPUINFO_INT_REGISTER + V60_R26:            info->i = cpustate->R26;                break;
  624          case CPUINFO_INT_REGISTER + V60_R27:            info->i = cpustate->R27;                break;
  625          case CPUINFO_INT_REGISTER + V60_R28:            info->i = cpustate->R28;                break;
  626          case CPUINFO_INT_REGISTER + V60_AP:             info->i = cpustate->AP;                 break;
  627          case CPUINFO_INT_REGISTER + V60_FP:             info->i = cpustate->FP;                 break;
  628          case CPUINFO_INT_SP:
  629          case CPUINFO_INT_REGISTER + V60_SP:             info->i = cpustate->SP;                 break;
  630          case CPUINFO_INT_PC:
  631          case CPUINFO_INT_REGISTER + V60_PC:             info->i = cpustate->PC;                 break;
  632          case CPUINFO_INT_REGISTER + V60_PSW:            info->i = v60ReadPSW(cpustate);         break;
  633          case CPUINFO_INT_REGISTER + V60_ISP:            info->i = cpustate->ISP;                break;
  634          case CPUINFO_INT_REGISTER + V60_L0SP:           info->i = cpustate->L0SP;               break;
  635          case CPUINFO_INT_REGISTER + V60_L1SP:           info->i = cpustate->L1SP;               break;
  636          case CPUINFO_INT_REGISTER + V60_L2SP:           info->i = cpustate->L2SP;               break;
  637          case CPUINFO_INT_REGISTER + V60_L3SP:           info->i = cpustate->L3SP;               break;
  638          case CPUINFO_INT_REGISTER + V60_SBR:            info->i = cpustate->SBR;                break;
  639          case CPUINFO_INT_REGISTER + V60_TR:             info->i = cpustate->TR;                 break;
  640          case CPUINFO_INT_REGISTER + V60_SYCW:           info->i = cpustate->SYCW;               break;
  641          case CPUINFO_INT_REGISTER + V60_TKCW:           info->i = cpustate->TKCW;               break;
  642          case CPUINFO_INT_REGISTER + V60_PIR:            info->i = cpustate->PIR;                break;
  643          case CPUINFO_INT_REGISTER + V60_PSW2:           info->i = cpustate->PSW2;               break;
  644          case CPUINFO_INT_REGISTER + V60_ATBR0:          info->i = cpustate->ATBR0;              break;
  645          case CPUINFO_INT_REGISTER + V60_ATLR0:          info->i = cpustate->ATLR0;              break;
  646          case CPUINFO_INT_REGISTER + V60_ATBR1:          info->i = cpustate->ATBR1;              break;
  647          case CPUINFO_INT_REGISTER + V60_ATLR1:          info->i = cpustate->ATLR1;              break;
  648          case CPUINFO_INT_REGISTER + V60_ATBR2:          info->i = cpustate->ATBR2;              break;
  649          case CPUINFO_INT_REGISTER + V60_ATLR2:          info->i = cpustate->ATLR2;              break;
  650          case CPUINFO_INT_REGISTER + V60_ATBR3:          info->i = cpustate->ATBR3;              break;
  651          case CPUINFO_INT_REGISTER + V60_ATLR3:          info->i = cpustate->ATLR3;              break;
  652          case CPUINFO_INT_REGISTER + V60_TRMODE:         info->i = cpustate->TRMODE;             break;
  653          case CPUINFO_INT_REGISTER + V60_ADTR0:          info->i = cpustate->ADTR0;              break;
  654          case CPUINFO_INT_REGISTER + V60_ADTR1:          info->i = cpustate->ADTR1;              break;
  655          case CPUINFO_INT_REGISTER + V60_ADTMR0:         info->i = cpustate->ADTMR0;             break;
  656          case CPUINFO_INT_REGISTER + V60_ADTMR1:         info->i = cpustate->ADTMR1;             break;
  657  
  658          /* --- the following bits of info are returned as pointers to data or functions --- */
  659          case CPUINFO_FCT_SET_INFO:                      info->setinfo = CPU_SET_INFO_NAME(v60);         break;
  660          case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(v60);                break;
  661          case CPUINFO_FCT_RESET:                         info->reset = CPU_RESET_NAME(v60);              break;
  662          case CPUINFO_FCT_EXIT:                          info->exit = CPU_EXIT_NAME(v60);                break;
  663          case CPUINFO_FCT_EXECUTE:                       info->execute = CPU_EXECUTE_NAME(v60);          break;
  664          case CPUINFO_FCT_BURN:                          info->burn = NULL;                              break;
  665          case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(v60);  break;
  666          case CPUINFO_PTR_INSTRUCTION_COUNTER:           info->icount = &cpustate->icount;               break;
  667  
  668          /* --- the following bits of info are returned as NULL-terminated strings --- */
  669          case CPUINFO_STR_NAME:                          strcpy(info->s, "V60");                 break;
  670          case CPUINFO_STR_FAMILY:                    strcpy(info->s, "NEC V60");             break;
  671          case CPUINFO_STR_VERSION:                   strcpy(info->s, "1.0");                 break;
  672          case CPUINFO_STR_SOURCE_FILE:                       strcpy(info->s, __FILE__);              break;
  673          case CPUINFO_STR_CREDITS:                   strcpy(info->s, "Farfetch'd and R.Belmont"); break;
  674  
  675          case CPUINFO_STR_FLAGS:                         strcpy(info->s, " ");                   break;
  676  
  677          case CPUINFO_STR_REGISTER + V60_R0:             sprintf(info->s, "R0:%08X", cpustate->R0);          break;
  678          case CPUINFO_STR_REGISTER + V60_R1:             sprintf(info->s, "R1:%08X", cpustate->R1);          break;
  679          case CPUINFO_STR_REGISTER + V60_R2:             sprintf(info->s, "R2:%08X", cpustate->R2);          break;
  680          case CPUINFO_STR_REGISTER + V60_R3:             sprintf(info->s, "R3:%08X", cpustate->R3);          break;
  681          case CPUINFO_STR_REGISTER + V60_R4:             sprintf(info->s, "R4:%08X", cpustate->R4);          break;
  682          case CPUINFO_STR_REGISTER + V60_R5:             sprintf(info->s, "R5:%08X", cpustate->R5);          break;
  683          case CPUINFO_STR_REGISTER + V60_R6:             sprintf(info->s, "R6:%08X", cpustate->R6);          break;
  684          case CPUINFO_STR_REGISTER + V60_R7:             sprintf(info->s, "R7:%08X", cpustate->R7);          break;
  685          case CPUINFO_STR_REGISTER + V60_R8:             sprintf(info->s, "R8:%08X", cpustate->R8);          break;
  686          case CPUINFO_STR_REGISTER + V60_R9:             sprintf(info->s, "R9:%08X", cpustate->R9);          break;
  687          case CPUINFO_STR_REGISTER + V60_R10:            sprintf(info->s, "R10:%08X", cpustate->R10);        break;
  688          case CPUINFO_STR_REGISTER + V60_R11:            sprintf(info->s, "R11:%08X", cpustate->R11);        break;
  689          case CPUINFO_STR_REGISTER + V60_R12:            sprintf(info->s, "R12:%08X", cpustate->R12);        break;
  690          case CPUINFO_STR_REGISTER + V60_R13:            sprintf(info->s, "R13:%08X", cpustate->R13);        break;
  691          case CPUINFO_STR_REGISTER + V60_R14:            sprintf(info->s, "R14:%08X", cpustate->R14);        break;
  692          case CPUINFO_STR_REGISTER + V60_R15:            sprintf(info->s, "R15:%08X", cpustate->R15);        break;
  693          case CPUINFO_STR_REGISTER + V60_R16:            sprintf(info->s, "R16:%08X", cpustate->R16);        break;
  694          case CPUINFO_STR_REGISTER + V60_R17:            sprintf(info->s, "R17:%08X", cpustate->R17);        break;
  695          case CPUINFO_STR_REGISTER + V60_R18:            sprintf(info->s, "R18:%08X", cpustate->R18);        break;
  696          case CPUINFO_STR_REGISTER + V60_R19:            sprintf(info->s, "R19:%08X", cpustate->R19);        break;
  697          case CPUINFO_STR_REGISTER + V60_R20:            sprintf(info->s, "R20:%08X", cpustate->R20);        break;
  698          case CPUINFO_STR_REGISTER + V60_R21:            sprintf(info->s, "R21:%08X", cpustate->R21);        break;
  699          case CPUINFO_STR_REGISTER + V60_R22:            sprintf(info->s, "R22:%08X", cpustate->R22);        break;
  700          case CPUINFO_STR_REGISTER + V60_R23:            sprintf(info->s, "R23:%08X", cpustate->R23);        break;
  701          case CPUINFO_STR_REGISTER + V60_R24:            sprintf(info->s, "R24:%08X", cpustate->R24);        break;
  702          case CPUINFO_STR_REGISTER + V60_R25:            sprintf(info->s, "R25:%08X", cpustate->R25);        break;
  703          case CPUINFO_STR_REGISTER + V60_R26:            sprintf(info->s, "R26:%08X", cpustate->R26);        break;
  704          case CPUINFO_STR_REGISTER + V60_R27:            sprintf(info->s, "R27:%08X", cpustate->R27);        break;
  705          case CPUINFO_STR_REGISTER + V60_R28:            sprintf(info->s, "R28:%08X", cpustate->R28);        break;
  706          case CPUINFO_STR_REGISTER + V60_AP:             sprintf(info->s, "AP:%08X", cpustate->AP);          break;
  707          case CPUINFO_STR_REGISTER + V60_FP:             sprintf(info->s, "FP:%08X", cpustate->FP);          break;
  708          case CPUINFO_STR_REGISTER + V60_SP:             sprintf(info->s, "SP:%08X", cpustate->SP);          break;
  709          case CPUINFO_STR_REGISTER + V60_PC:             sprintf(info->s, "PC:%08X", cpustate->PC);          break;
  710          case CPUINFO_STR_REGISTER + V60_PSW:            sprintf(info->s, "PSW:%08X", v60ReadPSW(cpustate)); break;
  711          case CPUINFO_STR_REGISTER + V60_ISP:            sprintf(info->s, "ISP:%08X", cpustate->ISP);        break;
  712          case CPUINFO_STR_REGISTER + V60_L0SP:           sprintf(info->s, "L0SP:%08X", cpustate->L0SP);      break;
  713          case CPUINFO_STR_REGISTER + V60_L1SP:           sprintf(info->s, "L1SP:%08X", cpustate->L1SP);      break;
  714          case CPUINFO_STR_REGISTER + V60_L2SP:           sprintf(info->s, "L2SP:%08X", cpustate->L2SP);      break;
  715          case CPUINFO_STR_REGISTER + V60_L3SP:           sprintf(info->s, "L3SP:%08X", cpustate->L3SP);      break;
  716          case CPUINFO_STR_REGISTER + V60_SBR:            sprintf(info->s, "SBR:%08X", cpustate->SBR);        break;
  717          case CPUINFO_STR_REGISTER + V60_TR:             sprintf(info->s, "TR:%08X", cpustate->TR);          break;
  718          case CPUINFO_STR_REGISTER + V60_SYCW:           sprintf(info->s, "SYCW:%08X", cpustate->SYCW);      break;
  719          case CPUINFO_STR_REGISTER + V60_TKCW:           sprintf(info->s, "TKCW:%08X", cpustate->TKCW);      break;
  720          case CPUINFO_STR_REGISTER + V60_PIR:            sprintf(info->s, "PIR:%08X", cpustate->PIR);        break;
  721          case CPUINFO_STR_REGISTER + V60_PSW2:           sprintf(info->s, "PSW2:%08X", cpustate->PSW2);      break;
  722          case CPUINFO_STR_REGISTER + V60_ATBR0:          sprintf(info->s, "ATBR0:%08X", cpustate->ATBR0);    break;
  723          case CPUINFO_STR_REGISTER + V60_ATLR0:          sprintf(info->s, "ATLR0:%08X", cpustate->ATLR0);    break;
  724          case CPUINFO_STR_REGISTER + V60_ATBR1:          sprintf(info->s, "ATBR1:%08X", cpustate->ATBR1);    break;
  725          case CPUINFO_STR_REGISTER + V60_ATLR1:          sprintf(info->s, "ATLR1:%08X", cpustate->ATLR1);    break;
  726          case CPUINFO_STR_REGISTER + V60_ATBR2:          sprintf(info->s, "ATBR2:%08X", cpustate->ATBR2);    break;
  727          case CPUINFO_STR_REGISTER + V60_ATLR2:          sprintf(info->s, "ATLR2:%08X", cpustate->ATLR2);    break;
  728          case CPUINFO_STR_REGISTER + V60_ATBR3:          sprintf(info->s, "ATBR3:%08X", cpustate->ATBR3);    break;
  729          case CPUINFO_STR_REGISTER + V60_ATLR3:          sprintf(info->s, "ATLR3:%08X", cpustate->ATLR3);    break;
  730          case CPUINFO_STR_REGISTER + V60_TRMODE:         sprintf(info->s, "TRMODE:%08X", cpustate->TRMODE);  break;
  731          case CPUINFO_STR_REGISTER + V60_ADTR0:          sprintf(info->s, "ADTR0:%08X", cpustate->ADTR0);    break;
  732          case CPUINFO_STR_REGISTER + V60_ADTR1:          sprintf(info->s, "ADTR1:%08X", cpustate->ADTR1);    break;
  733          case CPUINFO_STR_REGISTER + V60_ADTMR0:         sprintf(info->s, "ADTMR0:%08X", cpustate->ADTMR0);  break;
  734          case CPUINFO_STR_REGISTER + V60_ADTMR1:         sprintf(info->s, "ADTMR1:%08X", cpustate->ADTMR1);  break;
  735      }
  736  }
  737  
  738  
  739  /**************************************************************************
  740   * CPU-specific set_info
  741   **************************************************************************/
  742  
  743  CPU_GET_INFO( v70 )
  744  {
  745      switch (state)
  746      {
  747          /* --- the following bits of info are returned as 64-bit signed integers --- */
  748          case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:    info->i = 32;                   break;
  749          case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32;                  break;
  750          case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0;                   break;
  751  
  752          /* --- the following bits of info are returned as pointers to data or functions --- */
  753          case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(v70);                    break;
  754          case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(v70);          break;
  755  
  756          /* --- the following bits of info are returned as NULL-terminated strings --- */
  757          case CPUINFO_STR_NAME:                          strcpy(info->s, "V70");                 break;
  758  
  759          default:                                        CPU_GET_INFO_CALL(v60);                 break;
  760      }
  761  }
  762  
  763  DEFINE_LEGACY_CPU_DEVICE(V60, v60);
  764  DEFINE_LEGACY_CPU_DEVICE(V70, v70);