Viewing File: <root>/src/emu/sound/ymf262.c

    1  /*
    2  **
    3  ** File: ymf262.c - software implementation of YMF262
    4  **                  FM sound generator type OPL3
    5  **
    6  ** Copyright Jarek Burczynski
    7  **
    8  ** Version 0.2
    9  **
   10  
   11  Revision History:
   12  
   13  03-03-2003: initial release
   14   - thanks to Olivier Galibert and Chris Hardy for YMF262 and YAC512 chips
   15   - thanks to Stiletto for the datasheets
   16  
   17     Features as listed in 4MF262A6 data sheet:
   18      1. Registers are compatible with YM3812 (OPL2) FM sound source.
   19      2. Up to six sounds can be used as four-operator melody sounds for variety.
   20      3. 18 simultaneous melody sounds, or 15 melody sounds with 5 rhythm sounds (with two operators).
   21      4. 6 four-operator melody sounds and 6 two-operator melody sounds, or 6 four-operator melody
   22         sounds, 3 two-operator melody sounds and 5 rhythm sounds (with four operators).
   23      5. 8 selectable waveforms.
   24      6. 4-channel sound output.
   25      7. YMF262 compabile DAC (YAC512) is available.
   26      8. LFO for vibrato and tremolo effedts.
   27      9. 2 programable timers.
   28     10. Shorter register access time compared with YM3812.
   29     11. 5V single supply silicon gate CMOS process.
   30     12. 24 Pin SOP Package (YMF262-M), 48 Pin SQFP Package (YMF262-S).
   31  
   32  
   33  differences between OPL2 and OPL3 not documented in Yamaha datahasheets:
   34  - sinus table is a little different: the negative part is off by one...
   35  
   36  - in order to enable selection of four different waveforms on OPL2
   37    one must set bit 5 in register 0x01(test).
   38    on OPL3 this bit is ignored and 4-waveform select works *always*.
   39    (Don't confuse this with OPL3's 8-waveform select.)
   40  
   41  - Envelope Generator: all 15 x rates take zero time on OPL3
   42    (on OPL2 15 0 and 15 1 rates take some time while 15 2 and 15 3 rates
   43    take zero time)
   44  
   45  - channel calculations: output of operator 1 is in perfect sync with
   46    output of operator 2 on OPL3; on OPL and OPL2 output of operator 1
   47    is always delayed by one sample compared to output of operator 2
   48  
   49  
   50  differences between OPL2 and OPL3 shown in datasheets:
   51  - YMF262 does not support CSM mode
   52  
   53  
   54  */
   55  
   56  #include "emu.h"
   57  #include "ymf262.h"
   58  
   59  
   60  
   61  /* output final shift */
   62  #if (OPL3_SAMPLE_BITS==16)
   63      #define FINAL_SH    (0)
   64      #define MAXOUT      (+32767)
   65      #define MINOUT      (-32768)
   66  #else
   67      #define FINAL_SH    (8)
   68      #define MAXOUT      (+127)
   69      #define MINOUT      (-128)
   70  #endif
   71  
   72  
   73  #define FREQ_SH         16  /* 16.16 fixed point (frequency calculations) */
   74  #define EG_SH           16  /* 16.16 fixed point (EG timing)              */
   75  #define LFO_SH          24  /*  8.24 fixed point (LFO calculations)       */
   76  #define TIMER_SH        16  /* 16.16 fixed point (timers calculations)    */
   77  
   78  #define FREQ_MASK       ((1<<FREQ_SH)-1)
   79  
   80  /* envelope output entries */
   81  #define ENV_BITS        10
   82  #define ENV_LEN         (1<<ENV_BITS)
   83  #define ENV_STEP        (128.0/ENV_LEN)
   84  
   85  #define MAX_ATT_INDEX   ((1<<(ENV_BITS-1))-1) /*511*/
   86  #define MIN_ATT_INDEX   (0)
   87  
   88  /* sinwave entries */
   89  #define SIN_BITS        10
   90  #define SIN_LEN         (1<<SIN_BITS)
   91  #define SIN_MASK        (SIN_LEN-1)
   92  
   93  #define TL_RES_LEN      (256)   /* 8 bits addressing (real chip) */
   94  
   95  
   96  
   97  /* register number to channel number , slot offset */
   98  #define SLOT1 0
   99  #define SLOT2 1
  100  
  101  /* Envelope Generator phases */
  102  
  103  #define EG_ATT          4
  104  #define EG_DEC          3
  105  #define EG_SUS          2
  106  #define EG_REL          1
  107  #define EG_OFF          0
  108  
  109  
  110  /* save output as raw 16-bit sample */
  111  
  112  /*#define SAVE_SAMPLE*/
  113  
  114  #ifdef SAVE_SAMPLE
  115  static FILE *sample[1];
  116      #if 1   /*save to MONO file */
  117          #define SAVE_ALL_CHANNELS \
  118          {   signed int pom = a; \
  119              fputc((unsigned short)pom&0xff,sample[0]); \
  120              fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
  121          }
  122      #else   /*save to STEREO file */
  123          #define SAVE_ALL_CHANNELS \
  124          {   signed int pom = a; \
  125              fputc((unsigned short)pom&0xff,sample[0]); \
  126              fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
  127              pom = b; \
  128              fputc((unsigned short)pom&0xff,sample[0]); \
  129              fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
  130          }
  131      #endif
  132  #endif
  133  
  134  #define LOG_CYM_FILE 0
  135  static FILE * cymfile = NULL;
  136  
  137  
  138  
  139  
  140  
  141  #define OPL3_TYPE_YMF262 (0)    /* 36 operators, 8 waveforms */
  142  
  143  
  144  struct OPL3_SLOT
  145  {
  146      UINT32  ar;         /* attack rate: AR<<2           */
  147      UINT32  dr;         /* decay rate:  DR<<2           */
  148      UINT32  rr;         /* release rate:RR<<2           */
  149      UINT8   KSR;        /* key scale rate               */
  150      UINT8   ksl;        /* keyscale level               */
  151      UINT8   ksr;        /* key scale rate: kcode>>KSR   */
  152      UINT8   mul;        /* multiple: mul_tab[ML]        */
  153  
  154      /* Phase Generator */
  155      UINT32  Cnt;        /* frequency counter            */
  156      UINT32  Incr;       /* frequency counter step       */
  157      UINT8   FB;         /* feedback shift value         */
  158      INT32   *connect;   /* slot output pointer          */
  159      INT32   op1_out[2]; /* slot1 output for feedback    */
  160      UINT8   CON;        /* connection (algorithm) type  */
  161  
  162      /* Envelope Generator */
  163      UINT8   eg_type;    /* percussive/non-percussive mode */
  164      UINT8   state;      /* phase type                   */
  165      UINT32  TL;         /* total level: TL << 2         */
  166      INT32   TLL;        /* adjusted now TL              */
  167      INT32   volume;     /* envelope counter             */
  168      UINT32  sl;         /* sustain level: sl_tab[SL]    */
  169  
  170      UINT32  eg_m_ar;    /* (attack state)               */
  171      UINT8   eg_sh_ar;   /* (attack state)               */
  172      UINT8   eg_sel_ar;  /* (attack state)               */
  173      UINT32  eg_m_dr;    /* (decay state)                */
  174      UINT8   eg_sh_dr;   /* (decay state)                */
  175      UINT8   eg_sel_dr;  /* (decay state)                */
  176      UINT32  eg_m_rr;    /* (release state)              */
  177      UINT8   eg_sh_rr;   /* (release state)              */
  178      UINT8   eg_sel_rr;  /* (release state)              */
  179  
  180      UINT32  key;        /* 0 = KEY OFF, >0 = KEY ON     */
  181  
  182      /* LFO */
  183      UINT32  AMmask;     /* LFO Amplitude Modulation enable mask */
  184      UINT8   vib;        /* LFO Phase Modulation enable flag (active high)*/
  185  
  186      /* waveform select */
  187      UINT8   waveform_number;
  188      unsigned int wavetable;
  189  
  190  //unsigned char reserved[128-84];//speedup: pump up the struct size to power of 2
  191  unsigned char reserved[128-100];//speedup: pump up the struct size to power of 2
  192  
  193  };
  194  
  195  struct OPL3_CH
  196  {
  197      OPL3_SLOT SLOT[2];
  198  
  199      UINT32  block_fnum; /* block+fnum                   */
  200      UINT32  fc;         /* Freq. Increment base         */
  201      UINT32  ksl_base;   /* KeyScaleLevel Base step      */
  202      UINT8   kcode;      /* key code (for key scaling)   */
  203  
  204      /*
  205         there are 12 2-operator channels which can be combined in pairs
  206         to form six 4-operator channel, they are:
  207          0 and 3,
  208          1 and 4,
  209          2 and 5,
  210          9 and 12,
  211          10 and 13,
  212          11 and 14
  213      */
  214      UINT8   extended;   /* set to 1 if this channel forms up a 4op channel with another channel(only used by first of pair of channels, ie 0,1,2 and 9,10,11) */
  215  
  216  unsigned char reserved[512-272];//speedup:pump up the struct size to power of 2
  217  
  218  };
  219  
  220  /* OPL3 state */
  221  struct OPL3
  222  {
  223      OPL3_CH P_CH[18];               /* OPL3 chips have 18 channels  */
  224  
  225      UINT32  pan[18*4];              /* channels output masks (0xffffffff = enable); 4 masks per one channel */
  226      UINT32  pan_ctrl_value[18];     /* output control values 1 per one channel (1 value contains 4 masks) */
  227  
  228      signed int chanout[18];
  229      signed int phase_modulation;        /* phase modulation input (SLOT 2) */
  230      signed int phase_modulation2;   /* phase modulation input (SLOT 3 in 4 operator channels) */
  231  
  232      UINT32  eg_cnt;                 /* global envelope generator counter    */
  233      UINT32  eg_timer;               /* global envelope generator counter works at frequency = chipclock/288 (288=8*36) */
  234      UINT32  eg_timer_add;           /* step of eg_timer                     */
  235      UINT32  eg_timer_overflow;      /* envelope generator timer overlfows every 1 sample (on real chip) */
  236  
  237      UINT32  fn_tab[1024];           /* fnumber->increment counter   */
  238  
  239      /* LFO */
  240      UINT32  LFO_AM;
  241      INT32   LFO_PM;
  242  
  243      UINT8   lfo_am_depth;
  244      UINT8   lfo_pm_depth_range;
  245      UINT32  lfo_am_cnt;
  246      UINT32  lfo_am_inc;
  247      UINT32  lfo_pm_cnt;
  248      UINT32  lfo_pm_inc;
  249  
  250      UINT32  noise_rng;              /* 23 bit noise shift register  */
  251      UINT32  noise_p;                /* current noise 'phase'        */
  252      UINT32  noise_f;                /* current noise period         */
  253  
  254      UINT8   OPL3_mode;              /* OPL3 extension enable flag   */
  255  
  256      UINT8   rhythm;                 /* Rhythm mode                  */
  257  
  258      int     T[2];                   /* timer counters               */
  259      UINT8   st[2];                  /* timer enable                 */
  260  
  261      UINT32  address;                /* address register             */
  262      UINT8   status;                 /* status flag                  */
  263      UINT8   statusmask;             /* status mask                  */
  264  
  265      UINT8   nts;                    /* NTS (note select)            */
  266  
  267      /* external event callback handlers */
  268      OPL3_TIMERHANDLER  timer_handler;/* TIMER handler                */
  269      void *TimerParam;                   /* TIMER parameter              */
  270      OPL3_IRQHANDLER    IRQHandler;  /* IRQ handler                  */
  271      void *IRQParam;                 /* IRQ parameter                */
  272      OPL3_UPDATEHANDLER UpdateHandler;/* stream update handler       */
  273      void *UpdateParam;              /* stream update parameter      */
  274  
  275      UINT8 type;                     /* chip type                    */
  276      int clock;                      /* master clock  (Hz)           */
  277      int rate;                       /* sampling rate (Hz)           */
  278      double freqbase;                /* frequency base               */
  279      attotime TimerBase;         /* Timer base time (==sampling time)*/
  280      device_t *device;
  281  };
  282  
  283  
  284  
  285  /* mapping of register number (offset) to slot number used by the emulator */
  286  static const int slot_array[32]=
  287  {
  288          0, 2, 4, 1, 3, 5,-1,-1,
  289          6, 8,10, 7, 9,11,-1,-1,
  290      12,14,16,13,15,17,-1,-1,
  291      -1,-1,-1,-1,-1,-1,-1,-1
  292  };
  293  
  294  /* key scale level */
  295  /* table is 3dB/octave , DV converts this into 6dB/octave */
  296  /* 0.1875 is bit 0 weight of the envelope counter (volume) expressed in the 'decibel' scale */
  297  #define DV (0.1875/2.0)
  298  static const UINT32 ksl_tab[8*16]=
  299  {
  300      /* OCT 0 */
  301          0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
  302          0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
  303          0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
  304          0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
  305      /* OCT 1 */
  306          0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
  307          0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
  308          0.000/DV, 0.750/DV, 1.125/DV, 1.500/DV,
  309          1.875/DV, 2.250/DV, 2.625/DV, 3.000/DV,
  310      /* OCT 2 */
  311          0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
  312          0.000/DV, 1.125/DV, 1.875/DV, 2.625/DV,
  313          3.000/DV, 3.750/DV, 4.125/DV, 4.500/DV,
  314          4.875/DV, 5.250/DV, 5.625/DV, 6.000/DV,
  315      /* OCT 3 */
  316          0.000/DV, 0.000/DV, 0.000/DV, 1.875/DV,
  317          3.000/DV, 4.125/DV, 4.875/DV, 5.625/DV,
  318          6.000/DV, 6.750/DV, 7.125/DV, 7.500/DV,
  319          7.875/DV, 8.250/DV, 8.625/DV, 9.000/DV,
  320      /* OCT 4 */
  321          0.000/DV, 0.000/DV, 3.000/DV, 4.875/DV,
  322          6.000/DV, 7.125/DV, 7.875/DV, 8.625/DV,
  323          9.000/DV, 9.750/DV,10.125/DV,10.500/DV,
  324      10.875/DV,11.250/DV,11.625/DV,12.000/DV,
  325      /* OCT 5 */
  326          0.000/DV, 3.000/DV, 6.000/DV, 7.875/DV,
  327          9.000/DV,10.125/DV,10.875/DV,11.625/DV,
  328      12.000/DV,12.750/DV,13.125/DV,13.500/DV,
  329      13.875/DV,14.250/DV,14.625/DV,15.000/DV,
  330      /* OCT 6 */
  331          0.000/DV, 6.000/DV, 9.000/DV,10.875/DV,
  332      12.000/DV,13.125/DV,13.875/DV,14.625/DV,
  333      15.000/DV,15.750/DV,16.125/DV,16.500/DV,
  334      16.875/DV,17.250/DV,17.625/DV,18.000/DV,
  335      /* OCT 7 */
  336          0.000/DV, 9.000/DV,12.000/DV,13.875/DV,
  337      15.000/DV,16.125/DV,16.875/DV,17.625/DV,
  338      18.000/DV,18.750/DV,19.125/DV,19.500/DV,
  339      19.875/DV,20.250/DV,20.625/DV,21.000/DV
  340  };
  341  #undef DV
  342  
  343  /* sustain level table (3dB per step) */
  344  /* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
  345  #define SC(db) (UINT32) ( db * (2.0/ENV_STEP) )
  346  static const UINT32 sl_tab[16]={
  347      SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7),
  348      SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
  349  };
  350  #undef SC
  351  
  352  
  353  #define RATE_STEPS (8)
  354  static const unsigned char eg_inc[15*RATE_STEPS]={
  355  /*cycle:0 1  2 3  4 5  6 7*/
  356  
  357  /* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..12 0 (increment by 0 or 1) */
  358  /* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..12 1 */
  359  /* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..12 2 */
  360  /* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..12 3 */
  361  
  362  /* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 13 0 (increment by 1) */
  363  /* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 13 1 */
  364  /* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 13 2 */
  365  /* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 13 3 */
  366  
  367  /* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 14 0 (increment by 2) */
  368  /* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 14 1 */
  369  /*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 14 2 */
  370  /*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 14 3 */
  371  
  372  /*12 */ 4,4, 4,4, 4,4, 4,4, /* rates 15 0, 15 1, 15 2, 15 3 for decay */
  373  /*13 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 0, 15 1, 15 2, 15 3 for attack (zero time) */
  374  /*14 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
  375  };
  376  
  377  
  378  #define O(a) (a*RATE_STEPS)
  379  
  380  /* note that there is no O(13) in this table - it's directly in the code */
  381  static const unsigned char eg_rate_select[16+64+16]={   /* Envelope Generator rates (16 + 64 rates + 16 RKS) */
  382  /* 16 infinite time rates */
  383  O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
  384  O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
  385  
  386  /* rates 00-12 */
  387  O( 0),O( 1),O( 2),O( 3),
  388  O( 0),O( 1),O( 2),O( 3),
  389  O( 0),O( 1),O( 2),O( 3),
  390  O( 0),O( 1),O( 2),O( 3),
  391  O( 0),O( 1),O( 2),O( 3),
  392  O( 0),O( 1),O( 2),O( 3),
  393  O( 0),O( 1),O( 2),O( 3),
  394  O( 0),O( 1),O( 2),O( 3),
  395  O( 0),O( 1),O( 2),O( 3),
  396  O( 0),O( 1),O( 2),O( 3),
  397  O( 0),O( 1),O( 2),O( 3),
  398  O( 0),O( 1),O( 2),O( 3),
  399  O( 0),O( 1),O( 2),O( 3),
  400  
  401  /* rate 13 */
  402  O( 4),O( 5),O( 6),O( 7),
  403  
  404  /* rate 14 */
  405  O( 8),O( 9),O(10),O(11),
  406  
  407  /* rate 15 */
  408  O(12),O(12),O(12),O(12),
  409  
  410  /* 16 dummy rates (same as 15 3) */
  411  O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
  412  O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
  413  
  414  };
  415  #undef O
  416  
  417  /*rate  0,    1,    2,    3,   4,   5,   6,  7,  8,  9,  10, 11, 12, 13, 14, 15 */
  418  /*shift 12,   11,   10,   9,   8,   7,   6,  5,  4,  3,  2,  1,  0,  0,  0,  0  */
  419  /*mask  4095, 2047, 1023, 511, 255, 127, 63, 31, 15, 7,  3,  1,  0,  0,  0,  0  */
  420  
  421  #define O(a) (a*1)
  422  static const unsigned char eg_rate_shift[16+64+16]={    /* Envelope Generator counter shifts (16 + 64 rates + 16 RKS) */
  423  /* 16 infinite time rates */
  424  O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
  425  O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
  426  
  427  /* rates 00-12 */
  428  O(12),O(12),O(12),O(12),
  429  O(11),O(11),O(11),O(11),
  430  O(10),O(10),O(10),O(10),
  431  O( 9),O( 9),O( 9),O( 9),
  432  O( 8),O( 8),O( 8),O( 8),
  433  O( 7),O( 7),O( 7),O( 7),
  434  O( 6),O( 6),O( 6),O( 6),
  435  O( 5),O( 5),O( 5),O( 5),
  436  O( 4),O( 4),O( 4),O( 4),
  437  O( 3),O( 3),O( 3),O( 3),
  438  O( 2),O( 2),O( 2),O( 2),
  439  O( 1),O( 1),O( 1),O( 1),
  440  O( 0),O( 0),O( 0),O( 0),
  441  
  442  /* rate 13 */
  443  O( 0),O( 0),O( 0),O( 0),
  444  
  445  /* rate 14 */
  446  O( 0),O( 0),O( 0),O( 0),
  447  
  448  /* rate 15 */
  449  O( 0),O( 0),O( 0),O( 0),
  450  
  451  /* 16 dummy rates (same as 15 3) */
  452  O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
  453  O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
  454  
  455  };
  456  #undef O
  457  
  458  
  459  /* multiple table */
  460  #define ML 2
  461  static const UINT8 mul_tab[16]= {
  462  /* 1/2, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,10,12,12,15,15 */
  463      0.50*ML, 1.00*ML, 2.00*ML, 3.00*ML, 4.00*ML, 5.00*ML, 6.00*ML, 7.00*ML,
  464      8.00*ML, 9.00*ML,10.00*ML,10.00*ML,12.00*ML,12.00*ML,15.00*ML,15.00*ML
  465  };
  466  #undef ML
  467  
  468  /*  TL_TAB_LEN is calculated as:
  469  
  470  *   (12+1)=13 - sinus amplitude bits     (Y axis)
  471  *   additional 1: to compensate for calculations of negative part of waveform
  472  *   (if we don't add it then the greatest possible _negative_ value would be -2
  473  *   and we really need -1 for waveform #7)
  474  *   2  - sinus sign bit           (Y axis)
  475  *   TL_RES_LEN - sinus resolution (X axis)
  476  */
  477  #define TL_TAB_LEN (13*2*TL_RES_LEN)
  478  static signed int tl_tab[TL_TAB_LEN];
  479  
  480  #define ENV_QUIET       (TL_TAB_LEN>>4)
  481  
  482  /* sin waveform table in 'decibel' scale */
  483  /* there are eight waveforms on OPL3 chips */
  484  static unsigned int sin_tab[SIN_LEN * 8];
  485  
  486  
  487  /* LFO Amplitude Modulation table (verified on real YM3812)
  488     27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples
  489  
  490     Length: 210 elements.
  491  
  492      Each of the elements has to be repeated
  493      exactly 64 times (on 64 consecutive samples).
  494      The whole table takes: 64 * 210 = 13440 samples.
  495  
  496      When AM = 1 data is used directly
  497      When AM = 0 data is divided by 4 before being used (losing precision is important)
  498  */
  499  
  500  #define LFO_AM_TAB_ELEMENTS 210
  501  
  502  static const UINT8 lfo_am_table[LFO_AM_TAB_ELEMENTS] = {
  503  0,0,0,0,0,0,0,
  504  1,1,1,1,
  505  2,2,2,2,
  506  3,3,3,3,
  507  4,4,4,4,
  508  5,5,5,5,
  509  6,6,6,6,
  510  7,7,7,7,
  511  8,8,8,8,
  512  9,9,9,9,
  513  10,10,10,10,
  514  11,11,11,11,
  515  12,12,12,12,
  516  13,13,13,13,
  517  14,14,14,14,
  518  15,15,15,15,
  519  16,16,16,16,
  520  17,17,17,17,
  521  18,18,18,18,
  522  19,19,19,19,
  523  20,20,20,20,
  524  21,21,21,21,
  525  22,22,22,22,
  526  23,23,23,23,
  527  24,24,24,24,
  528  25,25,25,25,
  529  26,26,26,
  530  25,25,25,25,
  531  24,24,24,24,
  532  23,23,23,23,
  533  22,22,22,22,
  534  21,21,21,21,
  535  20,20,20,20,
  536  19,19,19,19,
  537  18,18,18,18,
  538  17,17,17,17,
  539  16,16,16,16,
  540  15,15,15,15,
  541  14,14,14,14,
  542  13,13,13,13,
  543  12,12,12,12,
  544  11,11,11,11,
  545  10,10,10,10,
  546  9,9,9,9,
  547  8,8,8,8,
  548  7,7,7,7,
  549  6,6,6,6,
  550  5,5,5,5,
  551  4,4,4,4,
  552  3,3,3,3,
  553  2,2,2,2,
  554  1,1,1,1
  555  };
  556  
  557  /* LFO Phase Modulation table (verified on real YM3812) */
  558  static const INT8 lfo_pm_table[8*8*2] = {
  559  /* FNUM2/FNUM = 00 0xxxxxxx (0x0000) */
  560  0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/
  561  0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 1*/
  562  
  563  /* FNUM2/FNUM = 00 1xxxxxxx (0x0080) */
  564  0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/
  565  1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 1*/
  566  
  567  /* FNUM2/FNUM = 01 0xxxxxxx (0x0100) */
  568  1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/
  569  2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 1*/
  570  
  571  /* FNUM2/FNUM = 01 1xxxxxxx (0x0180) */
  572  1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/
  573  3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 1*/
  574  
  575  /* FNUM2/FNUM = 10 0xxxxxxx (0x0200) */
  576  2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/
  577  4, 2, 0,-2,-4,-2, 0, 2, /*LFO PM depth = 1*/
  578  
  579  /* FNUM2/FNUM = 10 1xxxxxxx (0x0280) */
  580  2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/
  581  5, 2, 0,-2,-5,-2, 0, 2, /*LFO PM depth = 1*/
  582  
  583  /* FNUM2/FNUM = 11 0xxxxxxx (0x0300) */
  584  3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/
  585  6, 3, 0,-3,-6,-3, 0, 3, /*LFO PM depth = 1*/
  586  
  587  /* FNUM2/FNUM = 11 1xxxxxxx (0x0380) */
  588  3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/
  589  7, 3, 0,-3,-7,-3, 0, 3  /*LFO PM depth = 1*/
  590  };
  591  
  592  
  593  /* lock level of common table */
  594  static int num_lock = 0;
  595  
  596  /* work table */
  597  #define SLOT7_1 (&chip->P_CH[7].SLOT[SLOT1])
  598  #define SLOT7_2 (&chip->P_CH[7].SLOT[SLOT2])
  599  #define SLOT8_1 (&chip->P_CH[8].SLOT[SLOT1])
  600  #define SLOT8_2 (&chip->P_CH[8].SLOT[SLOT2])
  601  
  602  
  603  
  604  
  605  
  606  INLINE int limit( int val, int max, int min ) {
  607      if ( val > max )
  608          val = max;
  609      else if ( val < min )
  610          val = min;
  611  
  612      return val;
  613  }
  614  
  615  
  616  /* status set and IRQ handling */
  617  INLINE void OPL3_STATUS_SET(OPL3 *chip,int flag)
  618  {
  619      /* set status flag masking out disabled IRQs */
  620      chip->status |= (flag & chip->statusmask);
  621      if(!(chip->status & 0x80))
  622      {
  623          if(chip->status & 0x7f)
  624          {   /* IRQ on */
  625              chip->status |= 0x80;
  626              /* callback user interrupt handler (IRQ is OFF to ON) */
  627              if(chip->IRQHandler) (chip->IRQHandler)(chip->IRQParam,1);
  628          }
  629      }
  630  }
  631  
  632  /* status reset and IRQ handling */
  633  INLINE void OPL3_STATUS_RESET(OPL3 *chip,int flag)
  634  {
  635      /* reset status flag */
  636      chip->status &= ~flag;
  637      if(chip->status & 0x80)
  638      {
  639          if (!(chip->status & 0x7f))
  640          {
  641              chip->status &= 0x7f;
  642              /* callback user interrupt handler (IRQ is ON to OFF) */
  643              if(chip->IRQHandler) (chip->IRQHandler)(chip->IRQParam,0);
  644          }
  645      }
  646  }
  647  
  648  /* IRQ mask set */
  649  INLINE void OPL3_STATUSMASK_SET(OPL3 *chip,int flag)
  650  {
  651      chip->statusmask = flag;
  652      /* IRQ handling check */
  653      OPL3_STATUS_SET(chip,0);
  654      OPL3_STATUS_RESET(chip,0);
  655  }
  656  
  657  
  658  /* advance LFO to next sample */
  659  INLINE void advance_lfo(OPL3 *chip)
  660  {
  661      UINT8 tmp;
  662  
  663      /* LFO */
  664      chip->lfo_am_cnt += chip->lfo_am_inc;
  665      if (chip->lfo_am_cnt >= ((UINT32)LFO_AM_TAB_ELEMENTS<<LFO_SH) ) /* lfo_am_table is 210 elements long */
  666          chip->lfo_am_cnt -= ((UINT32)LFO_AM_TAB_ELEMENTS<<LFO_SH);
  667  
  668      tmp = lfo_am_table[ chip->lfo_am_cnt >> LFO_SH ];
  669  
  670      if (chip->lfo_am_depth)
  671          chip->LFO_AM = tmp;
  672      else
  673          chip->LFO_AM = tmp>>2;
  674  
  675      chip->lfo_pm_cnt += chip->lfo_pm_inc;
  676      chip->LFO_PM = ((chip->lfo_pm_cnt>>LFO_SH) & 7) | chip->lfo_pm_depth_range;
  677  }
  678  
  679  /* advance to next sample */
  680  INLINE void advance(OPL3 *chip)
  681  {
  682      OPL3_CH *CH;
  683      OPL3_SLOT *op;
  684      int i;
  685  
  686      chip->eg_timer += chip->eg_timer_add;
  687  
  688      while (chip->eg_timer >= chip->eg_timer_overflow)
  689      {
  690          chip->eg_timer -= chip->eg_timer_overflow;
  691  
  692          chip->eg_cnt++;
  693  
  694          for (i=0; i<9*2*2; i++)
  695          {
  696              CH  = &chip->P_CH[i/2];
  697              op  = &CH->SLOT[i&1];
  698  #if 1
  699              /* Envelope Generator */
  700              switch(op->state)
  701              {
  702              case EG_ATT:    /* attack phase */
  703  //              if ( !(chip->eg_cnt & ((1<<op->eg_sh_ar)-1) ) )
  704                  if ( !(chip->eg_cnt & op->eg_m_ar) )
  705                  {
  706                      op->volume += (~op->volume *
  707                                                  (eg_inc[op->eg_sel_ar + ((chip->eg_cnt>>op->eg_sh_ar)&7)])
  708                                                  ) >>3;
  709  
  710                      if (op->volume <= MIN_ATT_INDEX)
  711                      {
  712                          op->volume = MIN_ATT_INDEX;
  713                          op->state = EG_DEC;
  714                      }
  715  
  716                  }
  717              break;
  718  
  719              case EG_DEC:    /* decay phase */
  720  //              if ( !(chip->eg_cnt & ((1<<op->eg_sh_dr)-1) ) )
  721                  if ( !(chip->eg_cnt & op->eg_m_dr) )
  722                  {
  723                      op->volume += eg_inc[op->eg_sel_dr + ((chip->eg_cnt>>op->eg_sh_dr)&7)];
  724  
  725                      if ( op->volume >= op->sl )
  726                          op->state = EG_SUS;
  727  
  728                  }
  729              break;
  730  
  731              case EG_SUS:    /* sustain phase */
  732  
  733                  /* this is important behaviour:
  734                  one can change percusive/non-percussive modes on the fly and
  735                  the chip will remain in sustain phase - verified on real YM3812 */
  736  
  737                  if(op->eg_type)     /* non-percussive mode */
  738                  {
  739                                      /* do nothing */
  740                  }
  741                  else                /* percussive mode */
  742                  {
  743                      /* during sustain phase chip adds Release Rate (in percussive mode) */
  744  //                  if ( !(chip->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
  745                      if ( !(chip->eg_cnt & op->eg_m_rr) )
  746                      {
  747                          op->volume += eg_inc[op->eg_sel_rr + ((chip->eg_cnt>>op->eg_sh_rr)&7)];
  748  
  749                          if ( op->volume >= MAX_ATT_INDEX )
  750                              op->volume = MAX_ATT_INDEX;
  751                      }
  752                      /* else do nothing in sustain phase */
  753                  }
  754              break;
  755  
  756              case EG_REL:    /* release phase */
  757  //              if ( !(chip->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
  758                  if ( !(chip->eg_cnt & op->eg_m_rr) )
  759                  {
  760                      op->volume += eg_inc[op->eg_sel_rr + ((chip->eg_cnt>>op->eg_sh_rr)&7)];
  761  
  762                      if ( op->volume >= MAX_ATT_INDEX )
  763                      {
  764                          op->volume = MAX_ATT_INDEX;
  765                          op->state = EG_OFF;
  766                      }
  767  
  768                  }
  769              break;
  770  
  771              default:
  772              break;
  773              }
  774  #endif
  775          }
  776      }
  777  
  778      for (i=0; i<9*2*2; i++)
  779      {
  780          CH  = &chip->P_CH[i/2];
  781          op  = &CH->SLOT[i&1];
  782  
  783          /* Phase Generator */
  784          if(op->vib)
  785          {
  786              UINT8 block;
  787              unsigned int block_fnum = CH->block_fnum;
  788  
  789              unsigned int fnum_lfo   = (block_fnum&0x0380) >> 7;
  790  
  791              signed int lfo_fn_table_index_offset = lfo_pm_table[chip->LFO_PM + 16*fnum_lfo ];
  792  
  793              if (lfo_fn_table_index_offset)  /* LFO phase modulation active */
  794              {
  795                  block_fnum += lfo_fn_table_index_offset;
  796                  block = (block_fnum&0x1c00) >> 10;
  797                  op->Cnt += (chip->fn_tab[block_fnum&0x03ff] >> (7-block)) * op->mul;
  798              }
  799              else    /* LFO phase modulation  = zero */
  800              {
  801                  op->Cnt += op->Incr;
  802              }
  803          }
  804          else    /* LFO phase modulation disabled for this operator */
  805          {
  806              op->Cnt += op->Incr;
  807          }
  808      }
  809  
  810      /*  The Noise Generator of the YM3812 is 23-bit shift register.
  811      *   Period is equal to 2^23-2 samples.
  812      *   Register works at sampling frequency of the chip, so output
  813      *   can change on every sample.
  814      *
  815      *   Output of the register and input to the bit 22 is:
  816      *   bit0 XOR bit14 XOR bit15 XOR bit22
  817      *
  818      *   Simply use bit 22 as the noise output.
  819      */
  820  
  821      chip->noise_p += chip->noise_f;
  822      i = chip->noise_p >> FREQ_SH;       /* number of events (shifts of the shift register) */
  823      chip->noise_p &= FREQ_MASK;
  824      while (i)
  825      {
  826          /*
  827          UINT32 j;
  828          j = ( (chip->noise_rng) ^ (chip->noise_rng>>14) ^ (chip->noise_rng>>15) ^ (chip->noise_rng>>22) ) & 1;
  829          chip->noise_rng = (j<<22) | (chip->noise_rng>>1);
  830          */
  831  
  832          /*
  833              Instead of doing all the logic operations above, we
  834              use a trick here (and use bit 0 as the noise output).
  835              The difference is only that the noise bit changes one
  836              step ahead. This doesn't matter since we don't know
  837              what is real state of the noise_rng after the reset.
  838          */
  839  
  840          if (chip->noise_rng & 1) chip->noise_rng ^= 0x800302;
  841          chip->noise_rng >>= 1;
  842  
  843          i--;
  844      }
  845  }
  846  
  847  
  848  INLINE signed int op_calc(UINT32 phase, unsigned int env, signed int pm, unsigned int wave_tab)
  849  {
  850      UINT32 p;
  851  
  852      p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + (pm<<16))) >> FREQ_SH ) & SIN_MASK) ];
  853  
  854      if (p >= TL_TAB_LEN)
  855          return 0;
  856      return tl_tab[p];
  857  }
  858  
  859  INLINE signed int op_calc1(UINT32 phase, unsigned int env, signed int pm, unsigned int wave_tab)
  860  {
  861      UINT32 p;
  862  
  863      p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + pm))>>FREQ_SH) & SIN_MASK)];
  864  
  865      if (p >= TL_TAB_LEN)
  866          return 0;
  867      return tl_tab[p];
  868  }
  869  
  870  
  871  #define volume_calc(OP) ((OP)->TLL + ((UINT32)(OP)->volume) + (chip->LFO_AM & (OP)->AMmask))
  872  
  873  /* calculate output of a standard 2 operator channel
  874   (or 1st part of a 4-op channel) */
  875  INLINE void chan_calc( OPL3 *chip, OPL3_CH *CH )
  876  {
  877      OPL3_SLOT *SLOT;
  878      unsigned int env;
  879      signed int out;
  880  
  881      chip->phase_modulation = 0;
  882      chip->phase_modulation2= 0;
  883  
  884      /* SLOT 1 */
  885      SLOT = &CH->SLOT[SLOT1];
  886      env  = volume_calc(SLOT);
  887      out  = SLOT->op1_out[0] + SLOT->op1_out[1];
  888      SLOT->op1_out[0] = SLOT->op1_out[1];
  889      SLOT->op1_out[1] = 0;
  890      if( env < ENV_QUIET )
  891      {
  892          if (!SLOT->FB)
  893              out = 0;
  894          SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable );
  895      }
  896      *SLOT->connect += SLOT->op1_out[1];
  897  //logerror("out0=%5i vol0=%4i ", SLOT->op1_out[1], env );
  898  
  899      /* SLOT 2 */
  900      SLOT++;
  901      env = volume_calc(SLOT);
  902      if( env < ENV_QUIET )
  903          *SLOT->connect += op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable);
  904  
  905  //logerror("out1=%5i vol1=%4i\n", op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable), env );
  906  
  907  }
  908  
  909  /* calculate output of a 2nd part of 4-op channel */
  910  INLINE void chan_calc_ext( OPL3 *chip, OPL3_CH *CH )
  911  {
  912      OPL3_SLOT *SLOT;
  913      unsigned int env;
  914  
  915      chip->phase_modulation = 0;
  916  
  917      /* SLOT 1 */
  918      SLOT = &CH->SLOT[SLOT1];
  919      env  = volume_calc(SLOT);
  920      if( env < ENV_QUIET )
  921          *SLOT->connect += op_calc(SLOT->Cnt, env, chip->phase_modulation2, SLOT->wavetable );
  922  
  923      /* SLOT 2 */
  924      SLOT++;
  925      env = volume_calc(SLOT);
  926      if( env < ENV_QUIET )
  927          *SLOT->connect += op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable);
  928  
  929  }
  930  
  931  /*
  932      operators used in the rhythm sounds generation process:
  933  
  934      Envelope Generator:
  935  
  936  channel  operator  register number   Bass  High  Snare Tom  Top
  937  / slot   number    TL ARDR SLRR Wave Drum  Hat   Drum  Tom  Cymbal
  938   6 / 0   12        50  70   90   f0  +
  939   6 / 1   15        53  73   93   f3  +
  940   7 / 0   13        51  71   91   f1        +
  941   7 / 1   16        54  74   94   f4              +
  942   8 / 0   14        52  72   92   f2                    +
  943   8 / 1   17        55  75   95   f5                          +
  944  
  945      Phase Generator:
  946  
  947  channel  operator  register number   Bass  High  Snare Tom  Top
  948  / slot   number    MULTIPLE          Drum  Hat   Drum  Tom  Cymbal
  949   6 / 0   12        30                +
  950   6 / 1   15        33                +
  951   7 / 0   13        31                      +     +           +
  952   7 / 1   16        34                -----  n o t  u s e d -----
  953   8 / 0   14        32                                  +
  954   8 / 1   17        35                      +                 +
  955  
  956  channel  operator  register number   Bass  High  Snare Tom  Top
  957  number   number    BLK/FNUM2 FNUM    Drum  Hat   Drum  Tom  Cymbal
  958     6     12,15     B6        A6      +
  959  
  960     7     13,16     B7        A7            +     +           +
  961  
  962     8     14,17     B8        A8            +           +     +
  963  
  964  */
  965  
  966  /* calculate rhythm */
  967  
  968  INLINE void chan_calc_rhythm( OPL3 *chip, OPL3_CH *CH, unsigned int noise )
  969  {
  970      OPL3_SLOT *SLOT;
  971      signed int *chanout = chip->chanout;
  972      signed int out;
  973      unsigned int env;
  974  
  975  
  976      /* Bass Drum (verified on real YM3812):
  977        - depends on the channel 6 'connect' register:
  978            when connect = 0 it works the same as in normal (non-rhythm) mode (op1->op2->out)
  979            when connect = 1 _only_ operator 2 is present on output (op2->out), operator 1 is ignored
  980        - output sample always is multiplied by 2
  981      */
  982  
  983      chip->phase_modulation = 0;
  984  
  985      /* SLOT 1 */
  986      SLOT = &CH[6].SLOT[SLOT1];
  987      env = volume_calc(SLOT);
  988  
  989      out = SLOT->op1_out[0] + SLOT->op1_out[1];
  990      SLOT->op1_out[0] = SLOT->op1_out[1];
  991  
  992      if (!SLOT->CON)
  993          chip->phase_modulation = SLOT->op1_out[0];
  994      //else ignore output of operator 1
  995  
  996      SLOT->op1_out[1] = 0;
  997      if( env < ENV_QUIET )
  998      {
  999          if (!SLOT->FB)
 1000              out = 0;
 1001          SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable );
 1002      }
 1003  
 1004      /* SLOT 2 */
 1005      SLOT++;
 1006      env = volume_calc(SLOT);
 1007      if( env < ENV_QUIET )
 1008          chanout[6] += op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable) * 2;
 1009  
 1010  
 1011      /* Phase generation is based on: */
 1012      // HH  (13) channel 7->slot 1 combined with channel 8->slot 2 (same combination as TOP CYMBAL but different output phases)
 1013      // SD  (16) channel 7->slot 1
 1014      // TOM (14) channel 8->slot 1
 1015      // TOP (17) channel 7->slot 1 combined with channel 8->slot 2 (same combination as HIGH HAT but different output phases)
 1016  
 1017      /* Envelope generation based on: */
 1018      // HH  channel 7->slot1
 1019      // SD  channel 7->slot2
 1020      // TOM channel 8->slot1
 1021      // TOP channel 8->slot2
 1022  
 1023  
 1024      /* The following formulas can be well optimized.
 1025         I leave them in direct form for now (in case I've missed something).
 1026      */
 1027  
 1028      /* High Hat (verified on real YM3812) */
 1029      env = volume_calc(SLOT7_1);
 1030      if( env < ENV_QUIET )
 1031      {
 1032          /* high hat phase generation:
 1033              phase = d0 or 234 (based on frequency only)
 1034              phase = 34 or 2d0 (based on noise)
 1035          */
 1036  
 1037          /* base frequency derived from operator 1 in channel 7 */
 1038          unsigned char bit7 = ((SLOT7_1->Cnt>>FREQ_SH)>>7)&1;
 1039          unsigned char bit3 = ((SLOT7_1->Cnt>>FREQ_SH)>>3)&1;
 1040          unsigned char bit2 = ((SLOT7_1->Cnt>>FREQ_SH)>>2)&1;
 1041  
 1042          unsigned char res1 = (bit2 ^ bit7) | bit3;
 1043  
 1044          /* when res1 = 0 phase = 0x000 | 0xd0; */
 1045          /* when res1 = 1 phase = 0x200 | (0xd0>>2); */
 1046          UINT32 phase = res1 ? (0x200|(0xd0>>2)) : 0xd0;
 1047  
 1048          /* enable gate based on frequency of operator 2 in channel 8 */
 1049          unsigned char bit5e= ((SLOT8_2->Cnt>>FREQ_SH)>>5)&1;
 1050          unsigned char bit3e= ((SLOT8_2->Cnt>>FREQ_SH)>>3)&1;
 1051  
 1052          unsigned char res2 = (bit3e ^ bit5e);
 1053  
 1054          /* when res2 = 0 pass the phase from calculation above (res1); */
 1055          /* when res2 = 1 phase = 0x200 | (0xd0>>2); */
 1056          if (res2)
 1057              phase = (0x200|(0xd0>>2));
 1058  
 1059  
 1060          /* when phase & 0x200 is set and noise=1 then phase = 0x200|0xd0 */
 1061          /* when phase & 0x200 is set and noise=0 then phase = 0x200|(0xd0>>2), ie no change */
 1062          if (phase&0x200)
 1063          {
 1064              if (noise)
 1065                  phase = 0x200|0xd0;
 1066          }
 1067          else
 1068          /* when phase & 0x200 is clear and noise=1 then phase = 0xd0>>2 */
 1069          /* when phase & 0x200 is clear and noise=0 then phase = 0xd0, ie no change */
 1070          {
 1071              if (noise)
 1072                  phase = 0xd0>>2;
 1073          }
 1074  
 1075          chanout[7] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_1->wavetable) * 2;
 1076      }
 1077  
 1078      /* Snare Drum (verified on real YM3812) */
 1079      env = volume_calc(SLOT7_2);
 1080      if( env < ENV_QUIET )
 1081      {
 1082          /* base frequency derived from operator 1 in channel 7 */
 1083          unsigned char bit8 = ((SLOT7_1->Cnt>>FREQ_SH)>>8)&1;
 1084  
 1085          /* when bit8 = 0 phase = 0x100; */
 1086          /* when bit8 = 1 phase = 0x200; */
 1087          UINT32 phase = bit8 ? 0x200 : 0x100;
 1088  
 1089          /* Noise bit XOR'es phase by 0x100 */
 1090          /* when noisebit = 0 pass the phase from calculation above */
 1091          /* when noisebit = 1 phase ^= 0x100; */
 1092          /* in other words: phase ^= (noisebit<<8); */
 1093          if (noise)
 1094              phase ^= 0x100;
 1095  
 1096          chanout[7] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_2->wavetable) * 2;
 1097      }
 1098  
 1099      /* Tom Tom (verified on real YM3812) */
 1100      env = volume_calc(SLOT8_1);
 1101      if( env < ENV_QUIET )
 1102          chanout[8] += op_calc(SLOT8_1->Cnt, env, 0, SLOT8_1->wavetable) * 2;
 1103  
 1104      /* Top Cymbal (verified on real YM3812) */
 1105      env = volume_calc(SLOT8_2);
 1106      if( env < ENV_QUIET )
 1107      {
 1108          /* base frequency derived from operator 1 in channel 7 */
 1109          unsigned char bit7 = ((SLOT7_1->Cnt>>FREQ_SH)>>7)&1;
 1110          unsigned char bit3 = ((SLOT7_1->Cnt>>FREQ_SH)>>3)&1;
 1111          unsigned char bit2 = ((SLOT7_1->Cnt>>FREQ_SH)>>2)&1;
 1112  
 1113          unsigned char res1 = (bit2 ^ bit7) | bit3;
 1114  
 1115          /* when res1 = 0 phase = 0x000 | 0x100; */
 1116          /* when res1 = 1 phase = 0x200 | 0x100; */
 1117          UINT32 phase = res1 ? 0x300 : 0x100;
 1118  
 1119          /* enable gate based on frequency of operator 2 in channel 8 */
 1120          unsigned char bit5e= ((SLOT8_2->Cnt>>FREQ_SH)>>5)&1;
 1121          unsigned char bit3e= ((SLOT8_2->Cnt>>FREQ_SH)>>3)&1;
 1122  
 1123          unsigned char res2 = (bit3e ^ bit5e);
 1124          /* when res2 = 0 pass the phase from calculation above (res1); */
 1125          /* when res2 = 1 phase = 0x200 | 0x100; */
 1126          if (res2)
 1127              phase = 0x300;
 1128  
 1129          chanout[8] += op_calc(phase<<FREQ_SH, env, 0, SLOT8_2->wavetable) * 2;
 1130      }
 1131  
 1132  }
 1133  
 1134  
 1135  /* generic table initialize */
 1136  static int init_tables(void)
 1137  {
 1138      signed int i,x;
 1139      signed int n;
 1140      double o,m;
 1141  
 1142  
 1143      for (x=0; x<TL_RES_LEN; x++)
 1144      {
 1145          m = (1<<16) / pow(2, (x+1) * (ENV_STEP/4.0) / 8.0);
 1146          m = floor(m);
 1147  
 1148          /* we never reach (1<<16) here due to the (x+1) */
 1149          /* result fits within 16 bits at maximum */
 1150  
 1151          n = (int)m;     /* 16 bits here */
 1152          n >>= 4;        /* 12 bits here */
 1153          if (n&1)        /* round to nearest */
 1154              n = (n>>1)+1;
 1155          else
 1156              n = n>>1;
 1157                          /* 11 bits here (rounded) */
 1158          n <<= 1;        /* 12 bits here (as in real chip) */
 1159          tl_tab[ x*2 + 0 ] = n;
 1160          tl_tab[ x*2 + 1 ] = ~tl_tab[ x*2 + 0 ]; /* this *is* different from OPL2 (verified on real YMF262) */
 1161  
 1162          for (i=1; i<13; i++)
 1163          {
 1164              tl_tab[ x*2+0 + i*2*TL_RES_LEN ] =  tl_tab[ x*2+0 ]>>i;
 1165              tl_tab[ x*2+1 + i*2*TL_RES_LEN ] = ~tl_tab[ x*2+0 + i*2*TL_RES_LEN ];  /* this *is* different from OPL2 (verified on real YMF262) */
 1166          }
 1167      #if 0
 1168              logerror("tl %04i", x*2);
 1169              for (i=0; i<13; i++)
 1170                  logerror(", [%02i] %5i", i*2, tl_tab[ x*2 +0 + i*2*TL_RES_LEN ] ); /* positive */
 1171              logerror("\n");
 1172  
 1173              logerror("tl %04i", x*2);
 1174              for (i=0; i<13; i++)
 1175                  logerror(", [%02i] %5i", i*2, tl_tab[ x*2 +1 + i*2*TL_RES_LEN ] ); /* negative */
 1176              logerror("\n");
 1177      #endif
 1178      }
 1179  
 1180      for (i=0; i<SIN_LEN; i++)
 1181      {
 1182          /* non-standard sinus */
 1183          m = sin( ((i*2)+1) * M_PI / SIN_LEN ); /* checked against the real chip */
 1184  
 1185          /* we never reach zero here due to ((i*2)+1) */
 1186  
 1187          if (m>0.0)
 1188              o = 8*log(1.0/m)/log(2.0);  /* convert to 'decibels' */
 1189          else
 1190              o = 8*log(-1.0/m)/log(2.0); /* convert to 'decibels' */
 1191  
 1192          o = o / (ENV_STEP/4);
 1193  
 1194          n = (int)(2.0*o);
 1195          if (n&1)                        /* round to nearest */
 1196              n = (n>>1)+1;
 1197          else
 1198              n = n>>1;
 1199  
 1200          sin_tab[ i ] = n*2 + (m>=0.0? 0: 1 );
 1201  
 1202          /*logerror("YMF262.C: sin [%4i (hex=%03x)]= %4i (tl_tab value=%5i)\n", i, i, sin_tab[i], tl_tab[sin_tab[i]] );*/
 1203      }
 1204  
 1205      for (i=0; i<SIN_LEN; i++)
 1206      {
 1207          /* these 'pictures' represent _two_ cycles */
 1208          /* waveform 1:  __      __     */
 1209          /*             /  \____/  \____*/
 1210          /* output only first half of the sinus waveform (positive one) */
 1211  
 1212          if (i & (1<<(SIN_BITS-1)) )
 1213              sin_tab[1*SIN_LEN+i] = TL_TAB_LEN;
 1214          else
 1215              sin_tab[1*SIN_LEN+i] = sin_tab[i];
 1216  
 1217          /* waveform 2:  __  __  __  __ */
 1218          /*             /  \/  \/  \/  \*/
 1219          /* abs(sin) */
 1220  
 1221          sin_tab[2*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>1) ];
 1222  
 1223          /* waveform 3:  _   _   _   _  */
 1224          /*             / |_/ |_/ |_/ |_*/
 1225          /* abs(output only first quarter of the sinus waveform) */
 1226  
 1227          if (i & (1<<(SIN_BITS-2)) )
 1228              sin_tab[3*SIN_LEN+i] = TL_TAB_LEN;
 1229          else
 1230              sin_tab[3*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>2)];
 1231  
 1232          /* waveform 4:                 */
 1233          /*             /\  ____/\  ____*/
 1234          /*               \/      \/    */
 1235          /* output whole sinus waveform in half the cycle(step=2) and output 0 on the other half of cycle */
 1236  
 1237          if (i & (1<<(SIN_BITS-1)) )
 1238              sin_tab[4*SIN_LEN+i] = TL_TAB_LEN;
 1239          else
 1240              sin_tab[4*SIN_LEN+i] = sin_tab[i*2];
 1241  
 1242          /* waveform 5:                 */
 1243          /*             /\/\____/\/\____*/
 1244          /*                             */
 1245          /* output abs(whole sinus) waveform in half the cycle(step=2) and output 0 on the other half of cycle */
 1246  
 1247          if (i & (1<<(SIN_BITS-1)) )
 1248              sin_tab[5*SIN_LEN+i] = TL_TAB_LEN;
 1249          else
 1250              sin_tab[5*SIN_LEN+i] = sin_tab[(i*2) & (SIN_MASK>>1) ];
 1251  
 1252          /* waveform 6: ____    ____    */
 1253          /*                             */
 1254          /*                 ____    ____*/
 1255          /* output maximum in half the cycle and output minimum on the other half of cycle */
 1256  
 1257          if (i & (1<<(SIN_BITS-1)) )
 1258              sin_tab[6*SIN_LEN+i] = 1;   /* negative */
 1259          else
 1260              sin_tab[6*SIN_LEN+i] = 0;   /* positive */
 1261  
 1262          /* waveform 7:                 */
 1263          /*             |\____  |\____  */
 1264          /*                   \|      \|*/
 1265          /* output sawtooth waveform    */
 1266  
 1267          if (i & (1<<(SIN_BITS-1)) )
 1268              x = ((SIN_LEN-1)-i)*16 + 1; /* negative: from 8177 to 1 */
 1269          else
 1270              x = i*16;   /*positive: from 0 to 8176 */
 1271  
 1272          if (x > TL_TAB_LEN)
 1273              x = TL_TAB_LEN; /* clip to the allowed range */
 1274  
 1275          sin_tab[7*SIN_LEN+i] = x;
 1276  
 1277          //logerror("YMF262.C: sin1[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[1*SIN_LEN+i], tl_tab[sin_tab[1*SIN_LEN+i]] );
 1278          //logerror("YMF262.C: sin2[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[2*SIN_LEN+i], tl_tab[sin_tab[2*SIN_LEN+i]] );
 1279          //logerror("YMF262.C: sin3[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[3*SIN_LEN+i], tl_tab[sin_tab[3*SIN_LEN+i]] );
 1280          //logerror("YMF262.C: sin4[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[4*SIN_LEN+i], tl_tab[sin_tab[4*SIN_LEN+i]] );
 1281          //logerror("YMF262.C: sin5[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[5*SIN_LEN+i], tl_tab[sin_tab[5*SIN_LEN+i]] );
 1282          //logerror("YMF262.C: sin6[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[6*SIN_LEN+i], tl_tab[sin_tab[6*SIN_LEN+i]] );
 1283          //logerror("YMF262.C: sin7[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[7*SIN_LEN+i], tl_tab[sin_tab[7*SIN_LEN+i]] );
 1284      }
 1285      /*logerror("YMF262.C: ENV_QUIET= %08x (dec*8=%i)\n", ENV_QUIET, ENV_QUIET*8 );*/
 1286  
 1287  #ifdef SAVE_SAMPLE
 1288      sample[0]=fopen("sampsum.pcm","wb");
 1289  #endif
 1290  
 1291      return 1;
 1292  }
 1293  
 1294  static void OPLCloseTable( void )
 1295  {
 1296  #ifdef SAVE_SAMPLE
 1297      fclose(sample[0]);
 1298  #endif
 1299  }
 1300  
 1301  
 1302  
 1303  static void OPL3_initalize(OPL3 *chip)
 1304  {
 1305      int i;
 1306  
 1307      /* frequency base */
 1308      chip->freqbase  = (chip->rate) ? ((double)chip->clock / (8.0*36)) / chip->rate  : 0;
 1309  #if 0
 1310      chip->rate = (double)chip->clock / (8.0*36);
 1311      chip->freqbase  = 1.0;
 1312  #endif
 1313  
 1314      /* logerror("YMF262: freqbase=%f\n", chip->freqbase); */
 1315  
 1316      /* Timer base time */
 1317      chip->TimerBase = attotime::from_hz(chip->clock) * (8*36);
 1318  
 1319      /* make fnumber -> increment counter table */
 1320      for( i=0 ; i < 1024 ; i++ )
 1321      {
 1322          /* opn phase increment counter = 20bit */
 1323          chip->fn_tab[i] = (UINT32)( (double)i * 64 * chip->freqbase * (1<<(FREQ_SH-10)) ); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
 1324  #if 0
 1325          logerror("YMF262.C: fn_tab[%4i] = %08x (dec=%8i)\n",
 1326                      i, chip->fn_tab[i]>>6, chip->fn_tab[i]>>6 );
 1327  #endif
 1328      }
 1329  
 1330  #if 0
 1331      for( i=0 ; i < 16 ; i++ )
 1332      {
 1333          logerror("YMF262.C: sl_tab[%i] = %08x\n",
 1334              i, sl_tab[i] );
 1335      }
 1336      for( i=0 ; i < 8 ; i++ )
 1337      {
 1338          int j;
 1339          logerror("YMF262.C: ksl_tab[oct=%2i] =",i);
 1340          for (j=0; j<16; j++)
 1341          {
 1342              logerror("%08x ", ksl_tab[i*16+j] );
 1343          }
 1344          logerror("\n");
 1345      }
 1346  #endif
 1347  
 1348  
 1349      /* Amplitude modulation: 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples */
 1350      /* One entry from LFO_AM_TABLE lasts for 64 samples */
 1351      chip->lfo_am_inc = (1.0 / 64.0 ) * (1<<LFO_SH) * chip->freqbase;
 1352  
 1353      /* Vibrato: 8 output levels (triangle waveform); 1 level takes 1024 samples */
 1354      chip->lfo_pm_inc = (1.0 / 1024.0) * (1<<LFO_SH) * chip->freqbase;
 1355  
 1356      /*logerror ("chip->lfo_am_inc = %8x ; chip->lfo_pm_inc = %8x\n", chip->lfo_am_inc, chip->lfo_pm_inc);*/
 1357  
 1358      /* Noise generator: a step takes 1 sample */
 1359      chip->noise_f = (1.0 / 1.0) * (1<<FREQ_SH) * chip->freqbase;
 1360  
 1361      chip->eg_timer_add  = (1<<EG_SH)  * chip->freqbase;
 1362      chip->eg_timer_overflow = ( 1 ) * (1<<EG_SH);
 1363      /*logerror("YMF262init eg_timer_add=%8x eg_timer_overflow=%8x\n", chip->eg_timer_add, chip->eg_timer_overflow);*/
 1364  
 1365  }
 1366  
 1367  INLINE void FM_KEYON(OPL3_SLOT *SLOT, UINT32 key_set)
 1368  {
 1369      if( !SLOT->key )
 1370      {
 1371          /* restart Phase Generator */
 1372          SLOT->Cnt = 0;
 1373          /* phase -> Attack */
 1374          SLOT->state = EG_ATT;
 1375      }
 1376      SLOT->key |= key_set;
 1377  }
 1378  
 1379  INLINE void FM_KEYOFF(OPL3_SLOT *SLOT, UINT32 key_clr)
 1380  {
 1381      if( SLOT->key )
 1382      {
 1383          SLOT->key &= key_clr;
 1384  
 1385          if( !SLOT->key )
 1386          {
 1387              /* phase -> Release */
 1388              if (SLOT->state>EG_REL)
 1389                  SLOT->state = EG_REL;
 1390          }
 1391      }
 1392  }
 1393  
 1394  /* update phase increment counter of operator (also update the EG rates if necessary) */
 1395  INLINE void CALC_FCSLOT(OPL3_CH *CH,OPL3_SLOT *SLOT)
 1396  {
 1397      int ksr;
 1398  
 1399      /* (frequency) phase increment counter */
 1400      SLOT->Incr = CH->fc * SLOT->mul;
 1401      ksr = CH->kcode >> SLOT->KSR;
 1402  
 1403      if( SLOT->ksr != ksr )
 1404      {
 1405          SLOT->ksr = ksr;
 1406  
 1407          /* calculate envelope generator rates */
 1408          if ((SLOT->ar + SLOT->ksr) < 16+60)
 1409          {
 1410              SLOT->eg_sh_ar  = eg_rate_shift [SLOT->ar + SLOT->ksr ];
 1411              SLOT->eg_m_ar   = (1<<SLOT->eg_sh_ar)-1;
 1412              SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
 1413          }
 1414          else
 1415          {
 1416              SLOT->eg_sh_ar  = 0;
 1417              SLOT->eg_m_ar   = (1<<SLOT->eg_sh_ar)-1;
 1418              SLOT->eg_sel_ar = 13*RATE_STEPS;
 1419          }
 1420          SLOT->eg_sh_dr  = eg_rate_shift [SLOT->dr + SLOT->ksr ];
 1421          SLOT->eg_m_dr   = (1<<SLOT->eg_sh_dr)-1;
 1422          SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
 1423          SLOT->eg_sh_rr  = eg_rate_shift [SLOT->rr + SLOT->ksr ];
 1424          SLOT->eg_m_rr   = (1<<SLOT->eg_sh_rr)-1;
 1425          SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
 1426      }
 1427  }
 1428  
 1429  /* set multi,am,vib,EG-TYP,KSR,mul */
 1430  INLINE void set_mul(OPL3 *chip,int slot,int v)
 1431  {
 1432      OPL3_CH   *CH   = &chip->P_CH[slot/2];
 1433      OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
 1434  
 1435      SLOT->mul     = mul_tab[v&0x0f];
 1436      SLOT->KSR     = (v&0x10) ? 0 : 2;
 1437      SLOT->eg_type = (v&0x20);
 1438      SLOT->vib     = (v&0x40);
 1439      SLOT->AMmask  = (v&0x80) ? ~0 : 0;
 1440  
 1441      if (chip->OPL3_mode & 1)
 1442      {
 1443          int chan_no = slot/2;
 1444  
 1445          /* in OPL3 mode */
 1446          //DO THIS:
 1447          //if this is one of the slots of 1st channel forming up a 4-op channel
 1448          //do normal operation
 1449          //else normal 2 operator function
 1450          //OR THIS:
 1451          //if this is one of the slots of 2nd channel forming up a 4-op channel
 1452          //update it using channel data of 1st channel of a pair
 1453          //else normal 2 operator function
 1454          switch(chan_no)
 1455          {
 1456          case 0: case 1: case 2:
 1457          case 9: case 10: case 11:
 1458              if (CH->extended)
 1459              {
 1460                  /* normal */
 1461                  CALC_FCSLOT(CH,SLOT);
 1462              }
 1463              else
 1464              {
 1465                  /* normal */
 1466                  CALC_FCSLOT(CH,SLOT);
 1467              }
 1468          break;
 1469          case 3: case 4: case 5:
 1470          case 12: case 13: case 14:
 1471              if ((CH-3)->extended)
 1472              {
 1473                  /* update this SLOT using frequency data for 1st channel of a pair */
 1474                  CALC_FCSLOT(CH-3,SLOT);
 1475              }
 1476              else
 1477              {
 1478                  /* normal */
 1479                  CALC_FCSLOT(CH,SLOT);
 1480              }
 1481          break;
 1482          default:
 1483                  /* normal */
 1484                  CALC_FCSLOT(CH,SLOT);
 1485          break;
 1486          }
 1487      }
 1488      else
 1489      {
 1490          /* in OPL2 mode */
 1491          CALC_FCSLOT(CH,SLOT);
 1492      }
 1493  }
 1494  
 1495  /* set ksl & tl */
 1496  INLINE void set_ksl_tl(OPL3 *chip,int slot,int v)
 1497  {
 1498      OPL3_CH   *CH   = &chip->P_CH[slot/2];
 1499      OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
 1500  
 1501      int ksl = v>>6; /* 0 / 1.5 / 3.0 / 6.0 dB/OCT */
 1502  
 1503      SLOT->ksl = ksl ? 3-ksl : 31;
 1504      SLOT->TL  = (v&0x3f)<<(ENV_BITS-1-7); /* 7 bits TL (bit 6 = always 0) */
 1505  
 1506      if (chip->OPL3_mode & 1)
 1507      {
 1508          int chan_no = slot/2;
 1509  
 1510          /* in OPL3 mode */
 1511          //DO THIS:
 1512          //if this is one of the slots of 1st channel forming up a 4-op channel
 1513          //do normal operation
 1514          //else normal 2 operator function
 1515          //OR THIS:
 1516          //if this is one of the slots of 2nd channel forming up a 4-op channel
 1517          //update it using channel data of 1st channel of a pair
 1518          //else normal 2 operator function
 1519          switch(chan_no)
 1520          {
 1521          case 0: case 1: case 2:
 1522          case 9: case 10: case 11:
 1523              if (CH->extended)
 1524              {
 1525                  /* normal */
 1526                  SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
 1527              }
 1528              else
 1529              {
 1530                  /* normal */
 1531                  SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
 1532              }
 1533          break;
 1534          case 3: case 4: case 5:
 1535          case 12: case 13: case 14:
 1536              if ((CH-3)->extended)
 1537              {
 1538                  /* update this SLOT using frequency data for 1st channel of a pair */
 1539                  SLOT->TLL = SLOT->TL + ((CH-3)->ksl_base>>SLOT->ksl);
 1540              }
 1541              else
 1542              {
 1543                  /* normal */
 1544                  SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
 1545              }
 1546          break;
 1547          default:
 1548                  /* normal */
 1549                  SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
 1550          break;
 1551          }
 1552      }
 1553      else
 1554      {
 1555          /* in OPL2 mode */
 1556          SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
 1557      }
 1558  
 1559  }
 1560  
 1561  /* set attack rate & decay rate  */
 1562  INLINE void set_ar_dr(OPL3 *chip,int slot,int v)
 1563  {
 1564      OPL3_CH   *CH   = &chip->P_CH[slot/2];
 1565      OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
 1566  
 1567      SLOT->ar = (v>>4)  ? 16 + ((v>>4)  <<2) : 0;
 1568  
 1569      if ((SLOT->ar + SLOT->ksr) < 16+60) /* verified on real YMF262 - all 15 x rates take "zero" time */
 1570      {
 1571          SLOT->eg_sh_ar  = eg_rate_shift [SLOT->ar + SLOT->ksr ];
 1572          SLOT->eg_m_ar   = (1<<SLOT->eg_sh_ar)-1;
 1573          SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
 1574      }
 1575      else
 1576      {
 1577          SLOT->eg_sh_ar  = 0;
 1578          SLOT->eg_m_ar   = (1<<SLOT->eg_sh_ar)-1;
 1579          SLOT->eg_sel_ar = 13*RATE_STEPS;
 1580      }
 1581  
 1582      SLOT->dr    = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
 1583      SLOT->eg_sh_dr  = eg_rate_shift [SLOT->dr + SLOT->ksr ];
 1584      SLOT->eg_m_dr   = (1<<SLOT->eg_sh_dr)-1;
 1585      SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
 1586  }
 1587  
 1588  /* set sustain level & release rate */
 1589  INLINE void set_sl_rr(OPL3 *chip,int slot,int v)
 1590  {
 1591      OPL3_CH   *CH   = &chip->P_CH[slot/2];
 1592      OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
 1593  
 1594      SLOT->sl  = sl_tab[ v>>4 ];
 1595  
 1596      SLOT->rr  = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
 1597      SLOT->eg_sh_rr  = eg_rate_shift [SLOT->rr + SLOT->ksr ];
 1598      SLOT->eg_m_rr   = (1<<SLOT->eg_sh_rr)-1;
 1599      SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
 1600  }
 1601  
 1602  
 1603  static void update_channels(OPL3 *chip, OPL3_CH *CH)
 1604  {
 1605      /* update channel passed as a parameter and a channel at CH+=3; */
 1606      if (CH->extended)
 1607      {   /* we've just switched to combined 4 operator mode */
 1608  
 1609      }
 1610      else
 1611      {   /* we've just switched to normal 2 operator mode */
 1612  
 1613      }
 1614  
 1615  }
 1616  
 1617  /* write a value v to register r on OPL chip */
 1618  static void OPL3WriteReg(OPL3 *chip, int r, int v)
 1619  {
 1620      OPL3_CH *CH;
 1621      signed int *chanout = chip->chanout;
 1622      unsigned int ch_offset = 0;
 1623      int slot;
 1624      int block_fnum;
 1625  
 1626  
 1627  
 1628      if (LOG_CYM_FILE && (cymfile) && ((r&255)!=0) && (r!=255) )
 1629      {
 1630          if (r>0xff)
 1631              fputc( (unsigned char)0xff, cymfile );/*mark writes to second register set*/
 1632  
 1633          fputc( (unsigned char)r&0xff, cymfile );
 1634          fputc( (unsigned char)v, cymfile );
 1635      }
 1636  
 1637      if(r&0x100)
 1638      {
 1639          switch(r)
 1640          {
 1641          case 0x101: /* test register */
 1642              return;
 1643  
 1644          case 0x104: /* 6 channels enable */
 1645              {
 1646                  UINT8 prev;
 1647  
 1648                  CH = &chip->P_CH[0];    /* channel 0 */
 1649                  prev = CH->extended;
 1650                  CH->extended = (v>>0) & 1;
 1651                  if(prev != CH->extended)
 1652                      update_channels(chip, CH);
 1653                  CH++;                   /* channel 1 */
 1654                  prev = CH->extended;
 1655                  CH->extended = (v>>1) & 1;
 1656                  if(prev != CH->extended)
 1657                      update_channels(chip, CH);
 1658                  CH++;                   /* channel 2 */
 1659                  prev = CH->extended;
 1660                  CH->extended = (v>>2) & 1;
 1661                  if(prev != CH->extended)
 1662                      update_channels(chip, CH);
 1663  
 1664  
 1665                  CH = &chip->P_CH[9];    /* channel 9 */
 1666                  prev = CH->extended;
 1667                  CH->extended = (v>>3) & 1;
 1668                  if(prev != CH->extended)
 1669                      update_channels(chip, CH);
 1670                  CH++;                   /* channel 10 */
 1671                  prev = CH->extended;
 1672                  CH->extended = (v>>4) & 1;
 1673                  if(prev != CH->extended)
 1674                      update_channels(chip, CH);
 1675                  CH++;                   /* channel 11 */
 1676                  prev = CH->extended;
 1677                  CH->extended = (v>>5) & 1;
 1678                  if(prev != CH->extended)
 1679                      update_channels(chip, CH);
 1680  
 1681              }
 1682              return;
 1683  
 1684          case 0x105: /* OPL3 extensions enable register */
 1685  
 1686              chip->OPL3_mode = v&0x01;   /* OPL3 mode when bit0=1 otherwise it is OPL2 mode */
 1687  
 1688              /* following behaviour was tested on real YMF262,
 1689              switching OPL3/OPL2 modes on the fly:
 1690               - does not change the waveform previously selected (unless when ....)
 1691               - does not update CH.A, CH.B, CH.C and CH.D output selectors (registers c0-c8) (unless when ....)
 1692               - does not disable channels 9-17 on OPL3->OPL2 switch
 1693               - does not switch 4 operator channels back to 2 operator channels
 1694              */
 1695  
 1696              return;
 1697  
 1698          default:
 1699              if (r < 0x120)
 1700                  logerror("YMF262: write to unknown register (set#2): %03x value=%02x\n",r,v);
 1701          break;
 1702          }
 1703  
 1704          ch_offset = 9;  /* register page #2 starts from channel 9 (counting from 0) */
 1705      }
 1706  
 1707      /* adjust bus to 8 bits */
 1708      r &= 0xff;
 1709      v &= 0xff;
 1710  
 1711  
 1712      switch(r&0xe0)
 1713      {
 1714      case 0x00:  /* 00-1f:control */
 1715          switch(r&0x1f)
 1716          {
 1717          case 0x01:  /* test register */
 1718          break;
 1719          case 0x02:  /* Timer 1 */
 1720              chip->T[0] = (256-v)*4;
 1721          break;
 1722          case 0x03:  /* Timer 2 */
 1723              chip->T[1] = (256-v)*16;
 1724          break;
 1725          case 0x04:  /* IRQ clear / mask and Timer enable */
 1726              if(v&0x80)
 1727              {   /* IRQ flags clear */
 1728                  OPL3_STATUS_RESET(chip,0x60);
 1729              }
 1730              else
 1731              {   /* set IRQ mask ,timer enable */
 1732                  UINT8 st1 = v & 1;
 1733                  UINT8 st2 = (v>>1) & 1;
 1734  
 1735                  /* IRQRST,T1MSK,t2MSK,x,x,x,ST2,ST1 */
 1736                  OPL3_STATUS_RESET(chip, v & 0x60);
 1737                  OPL3_STATUSMASK_SET(chip, (~v) & 0x60 );
 1738  
 1739                  /* timer 2 */
 1740                  if(chip->st[1] != st2)
 1741                  {
 1742                      attotime period = st2 ? chip->TimerBase * chip->T[1] : attotime::zero;
 1743                      chip->st[1] = st2;
 1744                      if (chip->timer_handler) (chip->timer_handler)(chip->TimerParam,1,period);
 1745                  }
 1746                  /* timer 1 */
 1747                  if(chip->st[0] != st1)
 1748                  {
 1749                      attotime period = st1 ? chip->TimerBase * chip->T[0] : attotime::zero;
 1750                      chip->st[0] = st1;
 1751                      if (chip->timer_handler) (chip->timer_handler)(chip->TimerParam,0,period);
 1752                  }
 1753              }
 1754          break;
 1755          case 0x08:  /* x,NTS,x,x, x,x,x,x */
 1756              chip->nts = v;
 1757          break;
 1758  
 1759          default:
 1760              logerror("YMF262: write to unknown register: %02x value=%02x\n",r,v);
 1761          break;
 1762          }
 1763          break;
 1764      case 0x20:  /* am ON, vib ON, ksr, eg_type, mul */
 1765          slot = slot_array[r&0x1f];
 1766          if(slot < 0) return;
 1767          set_mul(chip, slot + ch_offset*2, v);
 1768      break;
 1769      case 0x40:
 1770          slot = slot_array[r&0x1f];
 1771          if(slot < 0) return;
 1772          set_ksl_tl(chip, slot + ch_offset*2, v);
 1773      break;
 1774      case 0x60:
 1775          slot = slot_array[r&0x1f];
 1776          if(slot < 0) return;
 1777          set_ar_dr(chip, slot + ch_offset*2, v);
 1778      break;
 1779      case 0x80:
 1780          slot = slot_array[r&0x1f];
 1781          if(slot < 0) return;
 1782          set_sl_rr(chip, slot + ch_offset*2, v);
 1783      break;
 1784      case 0xa0:
 1785          if (r == 0xbd)          /* am depth, vibrato depth, r,bd,sd,tom,tc,hh */
 1786          {
 1787              if (ch_offset != 0) /* 0xbd register is present in set #1 only */
 1788                  return;
 1789  
 1790              chip->lfo_am_depth = v & 0x80;
 1791              chip->lfo_pm_depth_range = (v&0x40) ? 8 : 0;
 1792  
 1793              chip->rhythm = v&0x3f;
 1794  
 1795              if(chip->rhythm&0x20)
 1796              {
 1797                  /* BD key on/off */
 1798                  if(v&0x10)
 1799                  {
 1800                      FM_KEYON (&chip->P_CH[6].SLOT[SLOT1], 2);
 1801                      FM_KEYON (&chip->P_CH[6].SLOT[SLOT2], 2);
 1802                  }
 1803                  else
 1804                  {
 1805                      FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT1],~2);
 1806                      FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT2],~2);
 1807                  }
 1808                  /* HH key on/off */
 1809                  if(v&0x01) FM_KEYON (&chip->P_CH[7].SLOT[SLOT1], 2);
 1810                  else       FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT1],~2);
 1811                  /* SD key on/off */
 1812                  if(v&0x08) FM_KEYON (&chip->P_CH[7].SLOT[SLOT2], 2);
 1813                  else       FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT2],~2);
 1814                  /* TOM key on/off */
 1815                  if(v&0x04) FM_KEYON (&chip->P_CH[8].SLOT[SLOT1], 2);
 1816                  else       FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT1],~2);
 1817                  /* TOP-CY key on/off */
 1818                  if(v&0x02) FM_KEYON (&chip->P_CH[8].SLOT[SLOT2], 2);
 1819                  else       FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT2],~2);
 1820              }
 1821              else
 1822              {
 1823                  /* BD key off */
 1824                  FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT1],~2);
 1825                  FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT2],~2);
 1826                  /* HH key off */
 1827                  FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT1],~2);
 1828                  /* SD key off */
 1829                  FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT2],~2);
 1830                  /* TOM key off */
 1831                  FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT1],~2);
 1832                  /* TOP-CY off */
 1833                  FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT2],~2);
 1834              }
 1835              return;
 1836          }
 1837  
 1838          /* keyon,block,fnum */
 1839          if( (r&0x0f) > 8) return;
 1840          CH = &chip->P_CH[(r&0x0f) + ch_offset];
 1841  
 1842          if(!(r&0x10))
 1843          {   /* a0-a8 */
 1844              block_fnum  = (CH->block_fnum&0x1f00) | v;
 1845          }
 1846          else
 1847          {   /* b0-b8 */
 1848              block_fnum = ((v&0x1f)<<8) | (CH->block_fnum&0xff);
 1849  
 1850              if (chip->OPL3_mode & 1)
 1851              {
 1852                  int chan_no = (r&0x0f) + ch_offset;
 1853  
 1854                  /* in OPL3 mode */
 1855                  //DO THIS:
 1856                  //if this is 1st channel forming up a 4-op channel
 1857                  //ALSO keyon/off slots of 2nd channel forming up 4-op channel
 1858                  //else normal 2 operator function keyon/off
 1859                  //OR THIS:
 1860                  //if this is 2nd channel forming up 4-op channel just do nothing
 1861                  //else normal 2 operator function keyon/off
 1862                  switch(chan_no)
 1863                  {
 1864                  case 0: case 1: case 2:
 1865                  case 9: case 10: case 11:
 1866                      if (CH->extended)
 1867                      {
 1868                          //if this is 1st channel forming up a 4-op channel
 1869                          //ALSO keyon/off slots of 2nd channel forming up 4-op channel
 1870                          if(v&0x20)
 1871                          {
 1872                              FM_KEYON (&CH->SLOT[SLOT1], 1);
 1873                              FM_KEYON (&CH->SLOT[SLOT2], 1);
 1874                              FM_KEYON (&(CH+3)->SLOT[SLOT1], 1);
 1875                              FM_KEYON (&(CH+3)->SLOT[SLOT2], 1);
 1876                          }
 1877                          else
 1878                          {
 1879                              FM_KEYOFF(&CH->SLOT[SLOT1],~1);
 1880                              FM_KEYOFF(&CH->SLOT[SLOT2],~1);
 1881                              FM_KEYOFF(&(CH+3)->SLOT[SLOT1],~1);
 1882                              FM_KEYOFF(&(CH+3)->SLOT[SLOT2],~1);
 1883                          }
 1884                      }
 1885                      else
 1886                      {
 1887                          //else normal 2 operator function keyon/off
 1888                          if(v&0x20)
 1889                          {
 1890                              FM_KEYON (&CH->SLOT[SLOT1], 1);
 1891                              FM_KEYON (&CH->SLOT[SLOT2], 1);
 1892                          }
 1893                          else
 1894                          {
 1895                              FM_KEYOFF(&CH->SLOT[SLOT1],~1);
 1896                              FM_KEYOFF(&CH->SLOT[SLOT2],~1);
 1897                          }
 1898                      }
 1899                  break;
 1900  
 1901                  case 3: case 4: case 5:
 1902                  case 12: case 13: case 14:
 1903                      if ((CH-3)->extended)
 1904                      {
 1905                          //if this is 2nd channel forming up 4-op channel just do nothing
 1906                      }
 1907                      else
 1908                      {
 1909                          //else normal 2 operator function keyon/off
 1910                          if(v&0x20)
 1911                          {
 1912                              FM_KEYON (&CH->SLOT[SLOT1], 1);
 1913                              FM_KEYON (&CH->SLOT[SLOT2], 1);
 1914                          }
 1915                          else
 1916                          {
 1917                              FM_KEYOFF(&CH->SLOT[SLOT1],~1);
 1918                              FM_KEYOFF(&CH->SLOT[SLOT2],~1);
 1919                          }
 1920                      }
 1921                  break;
 1922  
 1923                  default:
 1924                      if(v&0x20)
 1925                      {
 1926                          FM_KEYON (&CH->SLOT[SLOT1], 1);
 1927                          FM_KEYON (&CH->SLOT[SLOT2], 1);
 1928                      }
 1929                      else
 1930                      {
 1931                          FM_KEYOFF(&CH->SLOT[SLOT1],~1);
 1932                          FM_KEYOFF(&CH->SLOT[SLOT2],~1);
 1933                      }
 1934                  break;
 1935                  }
 1936              }
 1937              else
 1938              {
 1939                  if(v&0x20)
 1940                  {
 1941                      FM_KEYON (&CH->SLOT[SLOT1], 1);
 1942                      FM_KEYON (&CH->SLOT[SLOT2], 1);
 1943                  }
 1944                  else
 1945                  {
 1946                      FM_KEYOFF(&CH->SLOT[SLOT1],~1);
 1947                      FM_KEYOFF(&CH->SLOT[SLOT2],~1);
 1948                  }
 1949              }
 1950          }
 1951          /* update */
 1952          if(CH->block_fnum != block_fnum)
 1953          {
 1954              UINT8 block  = block_fnum >> 10;
 1955  
 1956              CH->block_fnum = block_fnum;
 1957  
 1958              CH->ksl_base = ksl_tab[block_fnum>>6];
 1959              CH->fc       = chip->fn_tab[block_fnum&0x03ff] >> (7-block);
 1960  
 1961              /* BLK 2,1,0 bits -> bits 3,2,1 of kcode */
 1962              CH->kcode    = (CH->block_fnum&0x1c00)>>9;
 1963  
 1964              /* the info below is actually opposite to what is stated in the Manuals (verifed on real YMF262) */
 1965              /* if notesel == 0 -> lsb of kcode is bit 10 (MSB) of fnum  */
 1966              /* if notesel == 1 -> lsb of kcode is bit 9 (MSB-1) of fnum */
 1967              if (chip->nts&0x40)
 1968                  CH->kcode |= (CH->block_fnum&0x100)>>8; /* notesel == 1 */
 1969              else
 1970                  CH->kcode |= (CH->block_fnum&0x200)>>9; /* notesel == 0 */
 1971  
 1972              if (chip->OPL3_mode & 1)
 1973              {
 1974                  int chan_no = (r&0x0f) + ch_offset;
 1975                  /* in OPL3 mode */
 1976                  //DO THIS:
 1977                  //if this is 1st channel forming up a 4-op channel
 1978                  //ALSO update slots of 2nd channel forming up 4-op channel
 1979                  //else normal 2 operator function keyon/off
 1980                  //OR THIS:
 1981                  //if this is 2nd channel forming up 4-op channel just do nothing
 1982                  //else normal 2 operator function keyon/off
 1983                  switch(chan_no)
 1984                  {
 1985                  case 0: case 1: case 2:
 1986                  case 9: case 10: case 11:
 1987                      if (CH->extended)
 1988                      {
 1989                          //if this is 1st channel forming up a 4-op channel
 1990                          //ALSO update slots of 2nd channel forming up 4-op channel
 1991  
 1992                          /* refresh Total Level in FOUR SLOTs of this channel and channel+3 using data from THIS channel */
 1993                          CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
 1994                          CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
 1995                          (CH+3)->SLOT[SLOT1].TLL = (CH+3)->SLOT[SLOT1].TL + (CH->ksl_base>>(CH+3)->SLOT[SLOT1].ksl);
 1996                          (CH+3)->SLOT[SLOT2].TLL = (CH+3)->SLOT[SLOT2].TL + (CH->ksl_base>>(CH+3)->SLOT[SLOT2].ksl);
 1997  
 1998                          /* refresh frequency counter in FOUR SLOTs of this channel and channel+3 using data from THIS channel */
 1999                          CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
 2000                          CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
 2001                          CALC_FCSLOT(CH,&(CH+3)->SLOT[SLOT1]);
 2002                          CALC_FCSLOT(CH,&(CH+3)->SLOT[SLOT2]);
 2003                      }
 2004                      else
 2005                      {
 2006                          //else normal 2 operator function
 2007                          /* refresh Total Level in both SLOTs of this channel */
 2008                          CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
 2009                          CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
 2010  
 2011                          /* refresh frequency counter in both SLOTs of this channel */
 2012                          CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
 2013                          CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
 2014                      }
 2015                  break;
 2016  
 2017                  case 3: case 4: case 5:
 2018                  case 12: case 13: case 14:
 2019                      if ((CH-3)->extended)
 2020                      {
 2021                          //if this is 2nd channel forming up 4-op channel just do nothing
 2022                      }
 2023                      else
 2024                      {
 2025                          //else normal 2 operator function
 2026                          /* refresh Total Level in both SLOTs of this channel */
 2027                          CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
 2028                          CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
 2029  
 2030                          /* refresh frequency counter in both SLOTs of this channel */
 2031                          CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
 2032                          CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
 2033                      }
 2034                  break;
 2035  
 2036                  default:
 2037                      /* refresh Total Level in both SLOTs of this channel */
 2038                      CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
 2039                      CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
 2040  
 2041                      /* refresh frequency counter in both SLOTs of this channel */
 2042                      CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
 2043                      CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
 2044                  break;
 2045                  }
 2046              }
 2047              else
 2048              {
 2049                  /* in OPL2 mode */
 2050  
 2051                  /* refresh Total Level in both SLOTs of this channel */
 2052                  CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
 2053                  CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
 2054  
 2055                  /* refresh frequency counter in both SLOTs of this channel */
 2056                  CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
 2057                  CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
 2058              }
 2059          }
 2060      break;
 2061  
 2062      case 0xc0:
 2063          /* CH.D, CH.C, CH.B, CH.A, FB(3bits), C */
 2064          if( (r&0xf) > 8) return;
 2065  
 2066          CH = &chip->P_CH[(r&0xf) + ch_offset];
 2067  
 2068          if( chip->OPL3_mode & 1 )
 2069          {
 2070              int base = ((r&0xf) + ch_offset) * 4;
 2071  
 2072              /* OPL3 mode */
 2073              chip->pan[ base    ] = (v & 0x10) ? ~0 : 0; /* ch.A */
 2074              chip->pan[ base +1 ] = (v & 0x20) ? ~0 : 0; /* ch.B */
 2075              chip->pan[ base +2 ] = (v & 0x40) ? ~0 : 0; /* ch.C */
 2076              chip->pan[ base +3 ] = (v & 0x80) ? ~0 : 0; /* ch.D */
 2077          }
 2078          else
 2079          {
 2080              int base = ((r&0xf) + ch_offset) * 4;
 2081  
 2082              /* OPL2 mode - always enabled */
 2083              chip->pan[ base    ] = ~0;      /* ch.A */
 2084              chip->pan[ base +1 ] = ~0;      /* ch.B */
 2085              chip->pan[ base +2 ] = ~0;      /* ch.C */
 2086              chip->pan[ base +3 ] = ~0;      /* ch.D */
 2087          }
 2088  
 2089          chip->pan_ctrl_value[ (r&0xf) + ch_offset ] = v;    /* store control value for OPL3/OPL2 mode switching on the fly */
 2090  
 2091          CH->SLOT[SLOT1].FB  = (v>>1)&7 ? ((v>>1)&7) + 7 : 0;
 2092          CH->SLOT[SLOT1].CON = v&1;
 2093  
 2094          if( chip->OPL3_mode & 1 )
 2095          {
 2096              int chan_no = (r&0x0f) + ch_offset;
 2097  
 2098              switch(chan_no)
 2099              {
 2100              case 0: case 1: case 2:
 2101              case 9: case 10: case 11:
 2102                  if (CH->extended)
 2103                  {
 2104                      UINT8 conn = (CH->SLOT[SLOT1].CON<<1) | ((CH+3)->SLOT[SLOT1].CON<<0);
 2105                      switch(conn)
 2106                      {
 2107                      case 0:
 2108                          /* 1 -> 2 -> 3 -> 4 - out */
 2109  
 2110                          CH->SLOT[SLOT1].connect = &chip->phase_modulation;
 2111                          CH->SLOT[SLOT2].connect = &chip->phase_modulation2;
 2112                          (CH+3)->SLOT[SLOT1].connect = &chip->phase_modulation;
 2113                          (CH+3)->SLOT[SLOT2].connect = &chanout[ chan_no + 3 ];
 2114                      break;
 2115                      case 1:
 2116                          /* 1 -> 2 -\
 2117                             3 -> 4 -+- out */
 2118  
 2119                          CH->SLOT[SLOT1].connect = &chip->phase_modulation;
 2120                          CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
 2121                          (CH+3)->SLOT[SLOT1].connect = &chip->phase_modulation;
 2122                          (CH+3)->SLOT[SLOT2].connect = &chanout[ chan_no + 3 ];
 2123                      break;
 2124                      case 2:
 2125                          /* 1 -----------\
 2126                             2 -> 3 -> 4 -+- out */
 2127  
 2128                          CH->SLOT[SLOT1].connect = &chanout[ chan_no ];
 2129                          CH->SLOT[SLOT2].connect = &chip->phase_modulation2;
 2130                          (CH+3)->SLOT[SLOT1].connect = &chip->phase_modulation;
 2131                          (CH+3)->SLOT[SLOT2].connect = &chanout[ chan_no + 3 ];
 2132                      break;
 2133                      case 3:
 2134                          /* 1 ------\
 2135                             2 -> 3 -+- out
 2136                             4 ------/     */
 2137                          CH->SLOT[SLOT1].connect = &chanout[ chan_no ];
 2138                          CH->SLOT[SLOT2].connect = &chip->phase_modulation2;
 2139                          (CH+3)->SLOT[SLOT1].connect = &chanout[ chan_no + 3 ];
 2140                          (CH+3)->SLOT[SLOT2].connect = &chanout[ chan_no + 3 ];
 2141                      break;
 2142                      }
 2143                  }
 2144                  else
 2145                  {
 2146                      /* 2 operators mode */
 2147                      CH->SLOT[SLOT1].connect = CH->SLOT[SLOT1].CON ? &chanout[(r&0xf)+ch_offset] : &chip->phase_modulation;
 2148                      CH->SLOT[SLOT2].connect = &chanout[(r&0xf)+ch_offset];
 2149                  }
 2150              break;
 2151  
 2152              case 3: case 4: case 5:
 2153              case 12: case 13: case 14:
 2154                  if ((CH-3)->extended)
 2155                  {
 2156                      UINT8 conn = ((CH-3)->SLOT[SLOT1].CON<<1) | (CH->SLOT[SLOT1].CON<<0);
 2157                      switch(conn)
 2158                      {
 2159                      case 0:
 2160                          /* 1 -> 2 -> 3 -> 4 - out */
 2161  
 2162                          (CH-3)->SLOT[SLOT1].connect = &chip->phase_modulation;
 2163                          (CH-3)->SLOT[SLOT2].connect = &chip->phase_modulation2;
 2164                          CH->SLOT[SLOT1].connect = &chip->phase_modulation;
 2165                          CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
 2166                      break;
 2167                      case 1:
 2168                          /* 1 -> 2 -\
 2169                             3 -> 4 -+- out */
 2170  
 2171                          (CH-3)->SLOT[SLOT1].connect = &chip->phase_modulation;
 2172                          (CH-3)->SLOT[SLOT2].connect = &chanout[ chan_no - 3 ];
 2173                          CH->SLOT[SLOT1].connect = &chip->phase_modulation;
 2174                          CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
 2175                      break;
 2176                      case 2:
 2177                          /* 1 -----------\
 2178                             2 -> 3 -> 4 -+- out */
 2179  
 2180                          (CH-3)->SLOT[SLOT1].connect = &chanout[ chan_no - 3 ];
 2181                          (CH-3)->SLOT[SLOT2].connect = &chip->phase_modulation2;
 2182                          CH->SLOT[SLOT1].connect = &chip->phase_modulation;
 2183                          CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
 2184                      break;
 2185                      case 3:
 2186                          /* 1 ------\
 2187                             2 -> 3 -+- out
 2188                             4 ------/     */
 2189                          (CH-3)->SLOT[SLOT1].connect = &chanout[ chan_no - 3 ];
 2190                          (CH-3)->SLOT[SLOT2].connect = &chip->phase_modulation2;
 2191                          CH->SLOT[SLOT1].connect = &chanout[ chan_no ];
 2192                          CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
 2193                      break;
 2194                      }
 2195                  }
 2196                  else
 2197                  {
 2198                      /* 2 operators mode */
 2199                      CH->SLOT[SLOT1].connect = CH->SLOT[SLOT1].CON ? &chanout[(r&0xf)+ch_offset] : &chip->phase_modulation;
 2200                      CH->SLOT[SLOT2].connect = &chanout[(r&0xf)+ch_offset];
 2201                  }
 2202              break;
 2203  
 2204              default:
 2205                      /* 2 operators mode */
 2206                      CH->SLOT[SLOT1].connect = CH->SLOT[SLOT1].CON ? &chanout[(r&0xf)+ch_offset] : &chip->phase_modulation;
 2207                      CH->SLOT[SLOT2].connect = &chanout[(r&0xf)+ch_offset];
 2208              break;
 2209              }
 2210          }
 2211          else
 2212          {
 2213              /* OPL2 mode - always 2 operators mode */
 2214              CH->SLOT[SLOT1].connect = CH->SLOT[SLOT1].CON ? &chanout[(r&0xf)+ch_offset] : &chip->phase_modulation;
 2215              CH->SLOT[SLOT2].connect = &chanout[(r&0xf)+ch_offset];
 2216          }
 2217      break;
 2218  
 2219      case 0xe0: /* waveform select */
 2220          slot = slot_array[r&0x1f];
 2221          if(slot < 0) return;
 2222  
 2223          slot += ch_offset*2;
 2224  
 2225          CH = &chip->P_CH[slot/2];
 2226  
 2227  
 2228          /* store 3-bit value written regardless of current OPL2 or OPL3 mode... (verified on real YMF262) */
 2229          v &= 7;
 2230          CH->SLOT[slot&1].waveform_number = v;
 2231  
 2232          /* ... but select only waveforms 0-3 in OPL2 mode */
 2233          if( !(chip->OPL3_mode & 1) )
 2234          {
 2235              v &= 3; /* we're in OPL2 mode */
 2236          }
 2237          CH->SLOT[slot&1].wavetable = v * SIN_LEN;
 2238      break;
 2239      }
 2240  }
 2241  
 2242  static TIMER_CALLBACK( cymfile_callback )
 2243  {
 2244      if (cymfile)
 2245      {
 2246          fputc( (unsigned char)0, cymfile );
 2247      }
 2248  }
 2249  
 2250  /* lock/unlock for common table */
 2251  static int OPL3_LockTable(device_t *device)
 2252  {
 2253      num_lock++;
 2254      if(num_lock>1) return 0;
 2255  
 2256      /* first time */
 2257  
 2258      if( !init_tables() )
 2259      {
 2260          num_lock--;
 2261          return -1;
 2262      }
 2263  
 2264      if (LOG_CYM_FILE)
 2265      {
 2266          cymfile = fopen("ymf262_.cym","wb");
 2267          if (cymfile)
 2268              device->machine().scheduler().timer_pulse ( attotime::from_hz(110), FUNC(cymfile_callback)); /*110 Hz pulse timer*/
 2269          else
 2270              logerror("Could not create ymf262_.cym file\n");
 2271      }
 2272  
 2273      return 0;
 2274  }
 2275  
 2276  static void OPL3_UnLockTable(void)
 2277  {
 2278      if(num_lock) num_lock--;
 2279      if(num_lock) return;
 2280  
 2281      /* last time */
 2282      OPLCloseTable();
 2283  
 2284      if (LOG_CYM_FILE)
 2285          fclose (cymfile);
 2286      cymfile = NULL;
 2287  }
 2288  
 2289  static void OPL3ResetChip(OPL3 *chip)
 2290  {
 2291      int c,s;
 2292  
 2293      chip->eg_timer = 0;
 2294      chip->eg_cnt   = 0;
 2295  
 2296      chip->noise_rng = 1;    /* noise shift register */
 2297      chip->nts       = 0;    /* note split */
 2298      OPL3_STATUS_RESET(chip,0x60);
 2299  
 2300      /* reset with register write */
 2301      OPL3WriteReg(chip,0x01,0); /* test register */
 2302      OPL3WriteReg(chip,0x02,0); /* Timer1 */
 2303      OPL3WriteReg(chip,0x03,0); /* Timer2 */
 2304      OPL3WriteReg(chip,0x04,0); /* IRQ mask clear */
 2305  
 2306  
 2307  //FIX IT  registers 101, 104 and 105
 2308  
 2309  
 2310  //FIX IT (dont change CH.D, CH.C, CH.B and CH.A in C0-C8 registers)
 2311      for(c = 0xff ; c >= 0x20 ; c-- )
 2312          OPL3WriteReg(chip,c,0);
 2313  //FIX IT (dont change CH.D, CH.C, CH.B and CH.A in C0-C8 registers)
 2314      for(c = 0x1ff ; c >= 0x120 ; c-- )
 2315          OPL3WriteReg(chip,c,0);
 2316  
 2317  
 2318  
 2319      /* reset operator parameters */
 2320      for( c = 0 ; c < 9*2 ; c++ )
 2321      {
 2322          OPL3_CH *CH = &chip->P_CH[c];
 2323          for(s = 0 ; s < 2 ; s++ )
 2324          {
 2325              CH->SLOT[s].state     = EG_OFF;
 2326              CH->SLOT[s].volume    = MAX_ATT_INDEX;
 2327          }
 2328      }
 2329  }
 2330  
 2331  /* Create one of virtual YMF262 */
 2332  /* 'clock' is chip clock in Hz  */
 2333  /* 'rate'  is sampling rate  */
 2334  static OPL3 *OPL3Create(device_t *device, int clock, int rate, int type)
 2335  {
 2336      OPL3 *chip;
 2337  
 2338      if (OPL3_LockTable(device) == -1) return NULL;
 2339  
 2340      /* allocate memory block */
 2341      chip = auto_alloc_clear(device->machine(), OPL3);
 2342  
 2343      chip->device = device;
 2344      chip->type  = type;
 2345      chip->clock = clock;
 2346      chip->rate  = rate;
 2347  
 2348      /* init global tables */
 2349      OPL3_initalize(chip);
 2350  
 2351      /* reset chip */
 2352      OPL3ResetChip(chip);
 2353      return chip;
 2354  }
 2355  
 2356  /* Destroy one of virtual YMF262 */
 2357  static void OPL3Destroy(OPL3 *chip)
 2358  {
 2359      OPL3_UnLockTable();
 2360      auto_free(chip->device->machine(), chip);
 2361  }
 2362  
 2363  
 2364  /* Optional handlers */
 2365  
 2366  static void OPL3SetTimerHandler(OPL3 *chip,OPL3_TIMERHANDLER timer_handler,void *param)
 2367  {
 2368      chip->timer_handler   = timer_handler;
 2369      chip->TimerParam = param;
 2370  }
 2371  static void OPL3SetIRQHandler(OPL3 *chip,OPL3_IRQHANDLER IRQHandler,void *param)
 2372  {
 2373      chip->IRQHandler     = IRQHandler;
 2374      chip->IRQParam = param;
 2375  }
 2376  static void OPL3SetUpdateHandler(OPL3 *chip,OPL3_UPDATEHANDLER UpdateHandler,void *param)
 2377  {
 2378      chip->UpdateHandler = UpdateHandler;
 2379      chip->UpdateParam = param;
 2380  }
 2381  
 2382  /* YMF262 I/O interface */
 2383  static int OPL3Write(OPL3 *chip, int a, int v)
 2384  {
 2385      /* data bus is 8 bits */
 2386      v &= 0xff;
 2387  
 2388      switch(a&3)
 2389      {
 2390      case 0: /* address port 0 (register set #1) */
 2391          chip->address = v;
 2392      break;
 2393  
 2394      case 1: /* data port - ignore A1 */
 2395      case 3: /* data port - ignore A1 */
 2396          if(chip->UpdateHandler) chip->UpdateHandler(chip->UpdateParam,0);
 2397          OPL3WriteReg(chip,chip->address,v);
 2398      break;
 2399  
 2400      case 2: /* address port 1 (register set #2) */
 2401  
 2402          /* verified on real YMF262:
 2403           in OPL3 mode:
 2404             address line A1 is stored during *address* write and ignored during *data* write.
 2405  
 2406           in OPL2 mode:
 2407             register set#2 writes go to register set#1 (ignoring A1)
 2408             verified on registers from set#2: 0x01, 0x04, 0x20-0xef
 2409             The only exception is register 0x05.
 2410          */
 2411          if( chip->OPL3_mode & 1 )
 2412          {
 2413              /* OPL3 mode */
 2414                  chip->address = v | 0x100;
 2415          }
 2416          else
 2417          {
 2418              /* in OPL2 mode the only accessible in set #2 is register 0x05 */
 2419              if( v==5 )
 2420                  chip->address = v | 0x100;
 2421              else
 2422                  chip->address = v;  /* verified range: 0x01, 0x04, 0x20-0xef(set #2 becomes set #1 in opl2 mode) */
 2423          }
 2424      break;
 2425      }
 2426  
 2427      return chip->status>>7;
 2428  }
 2429  
 2430  static unsigned char OPL3Read(OPL3 *chip,int a)
 2431  {
 2432      if( a==0 )
 2433      {
 2434          /* status port */
 2435          return chip->status;
 2436      }
 2437  
 2438      return 0x00;    /* verified on real YMF262 */
 2439  }
 2440  
 2441  
 2442  
 2443  static int OPL3TimerOver(OPL3 *chip,int c)
 2444  {
 2445      if( c )
 2446      {   /* Timer B */
 2447          OPL3_STATUS_SET(chip,0x20);
 2448      }
 2449      else
 2450      {   /* Timer A */
 2451          OPL3_STATUS_SET(chip,0x40);
 2452      }
 2453      /* reload timer */
 2454      if (chip->timer_handler) (chip->timer_handler)(chip->TimerParam,c,chip->TimerBase * chip->T[c]);
 2455      return chip->status>>7;
 2456  }
 2457  
 2458  
 2459  
 2460  
 2461  void * ymf262_init(device_t *device, int clock, int rate)
 2462  {
 2463      return OPL3Create(device,clock,rate,OPL3_TYPE_YMF262);
 2464  }
 2465  
 2466  void ymf262_shutdown(void *chip)
 2467  {
 2468      OPL3Destroy((OPL3 *)chip);
 2469  }
 2470  void ymf262_reset_chip(void *chip)
 2471  {
 2472      OPL3ResetChip((OPL3 *)chip);
 2473  }
 2474  
 2475  int ymf262_write(void *chip, int a, int v)
 2476  {
 2477      return OPL3Write((OPL3 *)chip, a, v);
 2478  }
 2479  
 2480  unsigned char ymf262_read(void *chip, int a)
 2481  {
 2482      /* Note on status register: */
 2483  
 2484      /* YM3526(OPL) and YM3812(OPL2) return bit2 and bit1 in HIGH state */
 2485  
 2486      /* YMF262(OPL3) always returns bit2 and bit1 in LOW state */
 2487      /* which can be used to identify the chip */
 2488  
 2489      /* YMF278(OPL4) returns bit2 in LOW and bit1 in HIGH state ??? info from manual - not verified */
 2490  
 2491      return OPL3Read((OPL3 *)chip, a);
 2492  }
 2493  int ymf262_timer_over(void *chip, int c)
 2494  {
 2495      return OPL3TimerOver((OPL3 *)chip, c);
 2496  }
 2497  
 2498  void ymf262_set_timer_handler(void *chip, OPL3_TIMERHANDLER timer_handler, void *param)
 2499  {
 2500      OPL3SetTimerHandler((OPL3 *)chip, timer_handler, param);
 2501  }
 2502  void ymf262_set_irq_handler(void *chip,OPL3_IRQHANDLER IRQHandler,void *param)
 2503  {
 2504      OPL3SetIRQHandler((OPL3 *)chip, IRQHandler, param);
 2505  }
 2506  void ymf262_set_update_handler(void *chip,OPL3_UPDATEHANDLER UpdateHandler,void *param)
 2507  {
 2508      OPL3SetUpdateHandler((OPL3 *)chip, UpdateHandler, param);
 2509  }
 2510  
 2511  
 2512  /*
 2513  ** Generate samples for one of the YMF262's
 2514  **
 2515  ** 'which' is the virtual YMF262 number
 2516  ** '**buffers' is table of 4 pointers to the buffers: CH.A, CH.B, CH.C and CH.D
 2517  ** 'length' is the number of samples that should be generated
 2518  */
 2519  void ymf262_update_one(void *_chip, OPL3SAMPLE **buffers, int length)
 2520  {
 2521      int i;
 2522      OPL3        *chip  = (OPL3 *)_chip;
 2523      signed int *chanout = chip->chanout;
 2524      UINT8       rhythm = chip->rhythm&0x20;
 2525  
 2526      OPL3SAMPLE  *ch_a = buffers[0];
 2527      OPL3SAMPLE  *ch_b = buffers[1];
 2528      OPL3SAMPLE  *ch_c = buffers[2];
 2529      OPL3SAMPLE  *ch_d = buffers[3];
 2530  
 2531      for( i=0; i < length ; i++ )
 2532      {
 2533          int a,b,c,d;
 2534  
 2535  
 2536          advance_lfo(chip);
 2537  
 2538          /* clear channel outputs */
 2539          memset(chip->chanout, 0, sizeof(chip->chanout));
 2540  
 2541  #if 1
 2542      /* register set #1 */
 2543          chan_calc(chip, &chip->P_CH[0]);            /* extended 4op ch#0 part 1 or 2op ch#0 */
 2544          if (chip->P_CH[0].extended)
 2545              chan_calc_ext(chip, &chip->P_CH[3]);    /* extended 4op ch#0 part 2 */
 2546          else
 2547              chan_calc(chip, &chip->P_CH[3]);        /* standard 2op ch#3 */
 2548  
 2549  
 2550          chan_calc(chip, &chip->P_CH[1]);            /* extended 4op ch#1 part 1 or 2op ch#1 */
 2551          if (chip->P_CH[1].extended)
 2552              chan_calc_ext(chip, &chip->P_CH[4]);    /* extended 4op ch#1 part 2 */
 2553          else
 2554              chan_calc(chip, &chip->P_CH[4]);        /* standard 2op ch#4 */
 2555  
 2556  
 2557          chan_calc(chip, &chip->P_CH[2]);            /* extended 4op ch#2 part 1 or 2op ch#2 */
 2558          if (chip->P_CH[2].extended)
 2559              chan_calc_ext(chip, &chip->P_CH[5]);    /* extended 4op ch#2 part 2 */
 2560          else
 2561              chan_calc(chip, &chip->P_CH[5]);        /* standard 2op ch#5 */
 2562  
 2563  
 2564          if(!rhythm)
 2565          {
 2566              chan_calc(chip, &chip->P_CH[6]);
 2567              chan_calc(chip, &chip->P_CH[7]);
 2568              chan_calc(chip, &chip->P_CH[8]);
 2569          }
 2570          else        /* Rhythm part */
 2571          {
 2572              chan_calc_rhythm(chip, &chip->P_CH[0], (chip->noise_rng>>0)&1 );
 2573          }
 2574  
 2575      /* register set #2 */
 2576          chan_calc(chip, &chip->P_CH[ 9]);
 2577          if (chip->P_CH[9].extended)
 2578              chan_calc_ext(chip, &chip->P_CH[12]);
 2579          else
 2580              chan_calc(chip, &chip->P_CH[12]);
 2581  
 2582  
 2583          chan_calc(chip, &chip->P_CH[10]);
 2584          if (chip->P_CH[10].extended)
 2585              chan_calc_ext(chip, &chip->P_CH[13]);
 2586          else
 2587              chan_calc(chip, &chip->P_CH[13]);
 2588  
 2589  
 2590          chan_calc(chip, &chip->P_CH[11]);
 2591          if (chip->P_CH[11].extended)
 2592              chan_calc_ext(chip, &chip->P_CH[14]);
 2593          else
 2594              chan_calc(chip, &chip->P_CH[14]);
 2595  
 2596  
 2597          /* channels 15,16,17 are fixed 2-operator channels only */
 2598          chan_calc(chip, &chip->P_CH[15]);
 2599          chan_calc(chip, &chip->P_CH[16]);
 2600          chan_calc(chip, &chip->P_CH[17]);
 2601  #endif
 2602  
 2603          /* accumulator register set #1 */
 2604          a =  chanout[0] & chip->pan[0];
 2605          b =  chanout[0] & chip->pan[1];
 2606          c =  chanout[0] & chip->pan[2];
 2607          d =  chanout[0] & chip->pan[3];
 2608  #if 1
 2609          a += chanout[1] & chip->pan[4];
 2610          b += chanout[1] & chip->pan[5];
 2611          c += chanout[1] & chip->pan[6];
 2612          d += chanout[1] & chip->pan[7];
 2613          a += chanout[2] & chip->pan[8];
 2614          b += chanout[2] & chip->pan[9];
 2615          c += chanout[2] & chip->pan[10];
 2616          d += chanout[2] & chip->pan[11];
 2617  
 2618          a += chanout[3] & chip->pan[12];
 2619          b += chanout[3] & chip->pan[13];
 2620          c += chanout[3] & chip->pan[14];
 2621          d += chanout[3] & chip->pan[15];
 2622          a += chanout[4] & chip->pan[16];
 2623          b += chanout[4] & chip->pan[17];
 2624          c += chanout[4] & chip->pan[18];
 2625          d += chanout[4] & chip->pan[19];
 2626          a += chanout[5] & chip->pan[20];
 2627          b += chanout[5] & chip->pan[21];
 2628          c += chanout[5] & chip->pan[22];
 2629          d += chanout[5] & chip->pan[23];
 2630  
 2631          a += chanout[6] & chip->pan[24];
 2632          b += chanout[6] & chip->pan[25];
 2633          c += chanout[6] & chip->pan[26];
 2634          d += chanout[6] & chip->pan[27];
 2635          a += chanout[7] & chip->pan[28];
 2636          b += chanout[7] & chip->pan[29];
 2637          c += chanout[7] & chip->pan[30];
 2638          d += chanout[7] & chip->pan[31];
 2639          a += chanout[8] & chip->pan[32];
 2640          b += chanout[8] & chip->pan[33];
 2641          c += chanout[8] & chip->pan[34];
 2642          d += chanout[8] & chip->pan[35];
 2643  
 2644          /* accumulator register set #2 */
 2645          a += chanout[9] & chip->pan[36];
 2646          b += chanout[9] & chip->pan[37];
 2647          c += chanout[9] & chip->pan[38];
 2648          d += chanout[9] & chip->pan[39];
 2649          a += chanout[10] & chip->pan[40];
 2650          b += chanout[10] & chip->pan[41];
 2651          c += chanout[10] & chip->pan[42];
 2652          d += chanout[10] & chip->pan[43];
 2653          a += chanout[11] & chip->pan[44];
 2654          b += chanout[11] & chip->pan[45];
 2655          c += chanout[11] & chip->pan[46];
 2656          d += chanout[11] & chip->pan[47];
 2657  
 2658          a += chanout[12] & chip->pan[48];
 2659          b += chanout[12] & chip->pan[49];
 2660          c += chanout[12] & chip->pan[50];
 2661          d += chanout[12] & chip->pan[51];
 2662          a += chanout[13] & chip->pan[52];
 2663          b += chanout[13] & chip->pan[53];
 2664          c += chanout[13] & chip->pan[54];
 2665          d += chanout[13] & chip->pan[55];
 2666          a += chanout[14] & chip->pan[56];
 2667          b += chanout[14] & chip->pan[57];
 2668          c += chanout[14] & chip->pan[58];
 2669          d += chanout[14] & chip->pan[59];
 2670  
 2671          a += chanout[15] & chip->pan[60];
 2672          b += chanout[15] & chip->pan[61];
 2673          c += chanout[15] & chip->pan[62];
 2674          d += chanout[15] & chip->pan[63];
 2675          a += chanout[16] & chip->pan[64];
 2676          b += chanout[16] & chip->pan[65];
 2677          c += chanout[16] & chip->pan[66];
 2678          d += chanout[16] & chip->pan[67];
 2679          a += chanout[17] & chip->pan[68];
 2680          b += chanout[17] & chip->pan[69];
 2681          c += chanout[17] & chip->pan[70];
 2682          d += chanout[17] & chip->pan[71];
 2683  #endif
 2684          a >>= FINAL_SH;
 2685          b >>= FINAL_SH;
 2686          c >>= FINAL_SH;
 2687          d >>= FINAL_SH;
 2688  
 2689          /* limit check */
 2690          a = limit( a , MAXOUT, MINOUT );
 2691          b = limit( b , MAXOUT, MINOUT );
 2692          c = limit( c , MAXOUT, MINOUT );
 2693          d = limit( d , MAXOUT, MINOUT );
 2694  
 2695          #ifdef SAVE_SAMPLE
 2696          if (which==0)
 2697          {
 2698              SAVE_ALL_CHANNELS
 2699          }
 2700          #endif
 2701  
 2702          /* store to sound buffer */
 2703          ch_a[i] = a;
 2704          ch_b[i] = b;
 2705          ch_c[i] = c;
 2706          ch_d[i] = d;
 2707  
 2708          advance(chip);
 2709      }
 2710  
 2711  }