Viewing File: <root>/src/mame/drivers/bfcobra.c

    1  /******************************************************************************
    2  
    3      Bell-Fruit Cobra I/II and Viper Hardware
    4  
    5      driver by Phil Bennett and Anonymous
    6  
    7      Games supported:
    8          * A Question of Sport [2 sets]
    9          * Beeline (non-working - missing disk)
   10          * Every Second Counts
   11          * Inquizitor (Viper hardware, non-working - missing disk)
   12          * Quizvaders
   13          * Treble Top
   14  
   15      Other games on this hardware:
   16          * Brain Box
   17          * Quintoon alt. version (Cobra II/Cyclone hardware)
   18  
   19      Notes:
   20  
   21      The hardware is based on a chipset known as 'Flare One', developed
   22      by Flare Technology. It consists of a 16-bit DSP (intended for sound
   23      synthesis and 3D maths), an 8bpp blitter and a video controller, driven
   24      by a Z80.
   25  
   26      Flare One would evolve to become 'Slipstream', used by the unreleased
   27      Konix Multisystem console.
   28  
   29      The Flare One chipset is implemented as four Texas Instruments ASICs,
   30      each an 84 pin PLCC package:
   31  
   32      CF30204, CF30205, CF30206 (DSP) and CF30207.
   33  
   34      The hardware using this chipset is as follows:
   35  
   36      Viper
   37      =====
   38  
   39      A video expansion PCB for Scorpion I?
   40      On some PCB revisions there is audio output circuitry connected to the DSP.
   41      Viper uses a WD1772 type floppy disk controller.
   42  
   43      Cobra I
   44      =======
   45  
   46      A combination of Viper and Scorpion I hardware on a single PCB.
   47      Cobra uses an NEC '765 type FDC. Later revisions have no DSP.
   48  
   49      Cobra II (Cyclone)
   50      ==================
   51  
   52      A compact video expansion board for Scorpion II.
   53      The Z80 is replaced by a Z180 and there is no Flare DSP or FDC
   54  
   55  
   56      To do:
   57  
   58      * Complete blitter emulation
   59      * Cobra II support
   60      * Hook up additional inputs, EM meters, lamps etc
   61  
   62      Known issues:
   63  
   64      * All games bar qos: NVRAM not saved
   65  
   66      * Viper does not have a colour palette - the Flare chipset drives RGB direct.
   67        To fix this I set default values in the palette when the machine is initialised
   68      * CPU execution rate is wrong, the hardware adds 1 TCycle to each access which is unaccounted for.
   69      * Plane priority is probably wrong but it's only used in Treble Top.
   70      * Blitter loop counts and step are wrong - they are 9 bit counts, not 8.
   71      * Blitter emulation doesn't support hi-res mode (needed for Inquizitor)
   72  
   73  ******************************************************************************/
   74  
   75  #include "emu.h"
   76  #include "machine/6850acia.h"
   77  #include "machine/meters.h"
   78  #include "cpu/z80/z80.h"
   79  #include "cpu/m6809/m6809.h"
   80  #include "sound/upd7759.h"
   81  #include "sound/ay8910.h"
   82  #include "machine/nvram.h"
   83  
   84  
   85  /*
   86      Defines
   87  */
   88  #define Z80_XTAL    5910000     /* Unconfirmed */
   89  #define M6809_XTAL  1000000
   90  
   91  
   92  /*
   93      Function prototypes
   94  */
   95  INLINE void z80_bank(running_machine &machine, int num, int data);
   96  
   97  
   98  /***************************************************************************
   99  
  100      Split into video\cobra.c !
  101  
  102  ***************************************************************************/
  103  
  104  union ADDR_REG
  105  {
  106  #ifdef LSB_FIRST
  107      struct { UINT16 loword, hiword ; } ;
  108      struct { UINT8 addr0, addr1, addr2; };
  109  #else
  110      struct { UINT16 hiword, loword ; } ;
  111      struct { UINT8 addr2, addr1, addr0; };
  112  #endif
  113      UINT32 addr;
  114  };
  115  
  116  /* Blitter register flag bits */
  117  #define CMD_RUN         0x01
  118  #define CMD_COLST       0x02
  119  #define CMD_PARRD       0x04        /* Never used? */
  120  #define CMD_SRCUP       0x08
  121  #define CMD_DSTUP       0x10
  122  #define CMD_LT0         0x20
  123  #define CMD_LT1         0x40
  124  #define CMD_LINEDRAW    0x80
  125  
  126  
  127  /* All unconfirmed */
  128  //#define SRCDST_CMP    0x10
  129  //#define SRCDST_WRAP   0x20
  130  //#define SRCDST_SIGN   0x40
  131  #define SRCDST_A_1      0x80        /* This might be correct for line drawing? */
  132  
  133  /* These appear to be correct */
  134  #define MODE_SSIGN      0x80
  135  #define MODE_DSIGN      0x40
  136  #define MODE_YFRAC      0x20
  137  #define MODE_BITTOBYTE  0x04
  138  #define MODE_PALREMAP   0x10
  139  
  140  #define CMPFUNC_LT      0x01
  141  #define CMPFUNC_EQ      0x02
  142  #define CMPFUNC_GT      0x04
  143  #define CMPFUNC_BEQ     0x08
  144  #define CMPFUNC_LOG0    0x10
  145  #define CMPFUNC_LOG1    0x20
  146  #define CMPFUNC_LOG2    0x40
  147  #define CMPFUNC_LOG3    0x80
  148  
  149  /*
  150      Blitter state
  151  */
  152  struct blitter_t
  153  {
  154      ADDR_REG    program;
  155  
  156      UINT8       control;
  157      UINT8       status;
  158  
  159      UINT8       command;
  160      ADDR_REG    source;
  161      ADDR_REG    dest;
  162      UINT8       modectl;
  163      UINT8       compfunc;
  164      UINT8       outercnt;
  165  
  166      UINT8       innercnt;
  167      UINT8       step;
  168      UINT8       pattern;
  169  };
  170  
  171  #define LOOPTYPE ( ( blitter.command&0x60 ) >> 5 )
  172  
  173  /*
  174      MUSIC Semiconductor TR9C1710 RAMDAC or equivalent
  175  */
  176  struct ramdac_t
  177  {
  178      UINT8   addr_w;
  179      UINT8   addr_r;
  180      UINT8   mask;
  181  
  182      /* 18-bit colors */
  183      UINT8   color_r[3];
  184      UINT8   color_w[3];
  185      UINT32  table[256];
  186  
  187      /* Access counts */
  188      UINT8   count_r;
  189      UINT8   count_w;
  190  };
  191  
  192  
  193  struct fdc_t
  194  {
  195      UINT8   MSR;
  196  
  197      int     side;
  198      int     track;
  199      int     sector;
  200      int     number;
  201      int     stop_track;
  202      int     setup_read;
  203  
  204      int     byte_pos;
  205      int     offset;
  206  
  207      int     phase;
  208      int     next_phase;
  209      int     cmd_len;
  210      int     cmd_cnt;
  211      int     res_len;
  212      int     res_cnt;
  213      UINT8   cmd[10];
  214      UINT8   results[8];
  215  };
  216  
  217  
  218  #define BLUE_0 0
  219  #define BLUE_1 1
  220  #define BLUE_2 2
  221  #define BLUE_3 3
  222  #define GREEN_0 ( 0 << 2 )
  223  #define GREEN_1 ( 1 << 2 )
  224  #define GREEN_2 ( 2 << 2 )
  225  #define GREEN_3 ( 3 << 2 )
  226  #define GREEN_4 ( 4 << 2 )
  227  #define GREEN_5 ( 5 << 2 )
  228  #define GREEN_6 ( 6 << 2 )
  229  #define GREEN_7 ( 7 << 2 )
  230  #define RED_0 ( 0 << 5 )
  231  #define RED_1 ( 1 << 5 )
  232  #define RED_2 ( 2 << 5 )
  233  #define RED_3 ( 3 << 5 )
  234  #define RED_4 ( 4 << 5 )
  235  #define RED_5 ( 5 << 5 )
  236  #define RED_6 ( 6 << 5 )
  237  #define RED_7 ( 7 << 5 )
  238  
  239  class bfcobra_state : public driver_device
  240  {
  241  public:
  242      bfcobra_state(const machine_config &mconfig, device_type type, const char *tag)
  243          : driver_device(mconfig, type, tag) { }
  244  
  245      UINT8 m_bank_data[4];
  246      UINT8 *m_work_ram;
  247      UINT8 *m_video_ram;
  248      UINT8 m_h_scroll;
  249      UINT8 m_v_scroll;
  250      UINT8 m_flip_8;
  251      UINT8 m_flip_22;
  252      UINT8 m_videomode;
  253      UINT8 m_z80_m6809_line;
  254      UINT8 m_m6809_z80_line;
  255      UINT8 m_data_r;
  256      UINT8 m_data_t;
  257      int m_irq_state;
  258      int m_acia_irq;
  259      int m_vblank_irq;
  260      int m_blitter_irq;
  261      UINT8 m_z80_int;
  262      UINT8 m_z80_inten;
  263      UINT32 m_meter_latch;
  264      UINT32 m_mux_input;
  265      UINT32 m_mux_outputlatch;
  266      UINT8 m_col4bit[16];
  267      UINT8 m_col3bit[16];
  268      UINT8 m_col8bit[256];
  269      UINT8 m_col7bit[256];
  270      UINT8 m_col6bit[256];
  271      struct blitter_t m_blitter;
  272      struct ramdac_t m_ramdac;
  273      struct fdc_t m_fdc;
  274      DECLARE_READ8_MEMBER(ramdac_r);
  275      DECLARE_WRITE8_MEMBER(ramdac_w);
  276      DECLARE_READ8_MEMBER(chipset_r);
  277      DECLARE_WRITE8_MEMBER(chipset_w);
  278      DECLARE_WRITE8_MEMBER(rombank_w);
  279      DECLARE_READ8_MEMBER(fdctrl_r);
  280      DECLARE_READ8_MEMBER(fddata_r);
  281      DECLARE_WRITE8_MEMBER(fdctrl_w);
  282      DECLARE_READ8_MEMBER(int_latch_r);
  283      DECLARE_READ8_MEMBER(meter_r);
  284      DECLARE_WRITE8_MEMBER(meter_w);
  285      DECLARE_READ8_MEMBER(latch_r);
  286      DECLARE_WRITE8_MEMBER(latch_w);
  287      DECLARE_WRITE8_MEMBER(fd_op_w);
  288      DECLARE_WRITE8_MEMBER(fd_ctrl_w);
  289      DECLARE_READ8_MEMBER(upd_r);
  290      DECLARE_WRITE8_MEMBER(upd_w);
  291      DECLARE_READ_LINE_MEMBER(z80_acia_rx_r);
  292      DECLARE_WRITE_LINE_MEMBER(z80_acia_tx_w);
  293      DECLARE_WRITE_LINE_MEMBER(z80_acia_irq);
  294      DECLARE_READ_LINE_MEMBER(m6809_acia_rx_r);
  295      DECLARE_WRITE_LINE_MEMBER(m6809_acia_tx_w);
  296      DECLARE_WRITE_LINE_MEMBER(m6809_data_irq);
  297      DECLARE_READ_LINE_MEMBER(data_acia_rx_r);
  298      DECLARE_WRITE_LINE_MEMBER(data_acia_tx_w);
  299      DECLARE_DRIVER_INIT(bfcobra);
  300      virtual void machine_reset();
  301      virtual void video_start();
  302      UINT32 screen_update_bfcobra(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
  303      INTERRUPT_GEN_MEMBER(timer_irq);
  304      INTERRUPT_GEN_MEMBER(vblank_gen);
  305      void RunBlit(address_space &space);
  306      void update_irqs();
  307      void reset_fdc();
  308      void exec_w_phase(UINT8 data);
  309      void init_ram();
  310      void command_phase(struct fdc_t &fdc, UINT8 data);
  311  };
  312  
  313  
  314  static const UINT8 col4bit_default[16]=
  315  {
  316      BLUE_0 | GREEN_0 | RED_0,
  317      BLUE_1,
  318      GREEN_2,
  319      BLUE_1 | GREEN_2,
  320      RED_2,
  321      RED_2 | BLUE_1,
  322      RED_2 | GREEN_2,
  323      RED_2 | GREEN_2 | BLUE_1,
  324      BLUE_2 | GREEN_5 | RED_5,
  325      BLUE_3,
  326      GREEN_7,
  327      BLUE_3 | GREEN_7,
  328      RED_7,
  329      RED_7 | BLUE_3,
  330      RED_7 | GREEN_7,
  331      RED_7 | GREEN_7 | BLUE_3
  332  };
  333  
  334  static const UINT8 col3bit_default[16]=
  335  {
  336      0,
  337      BLUE_3,
  338      GREEN_7,
  339      BLUE_3 | GREEN_7,
  340      RED_7,
  341      RED_7 | BLUE_3,
  342      RED_7 | GREEN_7,
  343      RED_7 | GREEN_7 | BLUE_3,
  344      0,
  345      BLUE_3,
  346      GREEN_7,
  347      BLUE_3 | GREEN_7,
  348      RED_7,
  349      RED_7 | BLUE_3,
  350      RED_7 | GREEN_7,
  351      RED_7 | GREEN_7 | BLUE_3
  352  };
  353  
  354  static const UINT8 col76index[] = {0, 2, 4, 7};
  355  
  356  
  357  void bfcobra_state::video_start()
  358  {
  359      int i;
  360  
  361      memcpy(m_col4bit, col4bit_default, sizeof(m_col4bit));
  362      memcpy(m_col3bit, col3bit_default, sizeof(m_col3bit));
  363      for (i = 0; i < 256; ++i)
  364      {
  365          UINT8 col;
  366  
  367          m_col8bit[i] = i;
  368          col = i & 0x7f;
  369          col = (col & 0x1f) | (col76index[ ( (col & 0x60) >> 5 ) & 3] << 5);
  370          m_col7bit[i] = col;
  371  
  372          col = (col & 3) | (col76index[( (col & 0x0c) >> 2) & 3] << 2 ) |
  373                  (col76index[( (col & 0x30) >> 4) & 3] << 5 );
  374          m_col6bit[i] = col;
  375      }
  376  }
  377  
  378  UINT32 bfcobra_state::screen_update_bfcobra(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
  379  {
  380      int x, y;
  381      UINT8  *src;
  382      UINT32 *dest;
  383      UINT32 offset;
  384      UINT8 *hirescol;
  385      UINT8 *lorescol;
  386  
  387      /* Select screen has to be programmed into two registers */
  388      /* No idea what happens if the registers are different */
  389      if (m_flip_8 & 0x40 && m_flip_22 & 0x40)
  390          offset = 0x10000;
  391      else
  392          offset = 0;
  393  
  394      if(m_videomode & 0x20)
  395      {
  396          hirescol = m_col3bit;
  397          lorescol = m_col7bit;
  398      }
  399      else if(m_videomode & 0x40)
  400      {
  401          hirescol = m_col4bit;
  402          lorescol = m_col6bit;
  403      }
  404      else
  405      {
  406          hirescol = m_col4bit;
  407          lorescol = m_col8bit;
  408      }
  409  
  410      for (y = cliprect.min_y; y <= cliprect.max_y; ++y)
  411      {
  412          UINT16 y_offset = (y + m_v_scroll) * 256;
  413          src = &m_video_ram[offset + y_offset];
  414          dest = &bitmap.pix32(y);
  415  
  416          for (x = cliprect.min_x; x <= cliprect.max_x / 2; ++x)
  417          {
  418              UINT8 x_offset = x + m_h_scroll;
  419              UINT8 pen = *(src + x_offset);
  420  
  421              if ( ( m_videomode & 0x81 ) == 1 || (m_videomode & 0x80 && pen & 0x80) )
  422              {
  423                  *dest++ = machine().pens[hirescol[pen & 0x0f]];
  424                  *dest++ = machine().pens[hirescol[(pen >> 4) & 0x0f]];
  425              }
  426              else
  427              {
  428                  *dest++ = machine().pens[lorescol[pen]];
  429                  *dest++ = machine().pens[lorescol[pen]];
  430              }
  431          }
  432      }
  433  
  434      return 0;
  435  }
  436  
  437  INLINE UINT8* blitter_get_addr(running_machine &machine, UINT32 addr)
  438  {
  439      bfcobra_state *state = machine.driver_data<bfcobra_state>();
  440      if (addr < 0x10000)
  441      {
  442          /* Is this region fixed? */
  443          return (UINT8*)(state->memregion("user1")->base() + addr);
  444      }
  445      else if(addr < 0x20000)
  446      {
  447          addr &= 0xffff;
  448          addr += (state->m_bank_data[0] & 1) ? 0x10000 : 0;
  449  
  450          return (UINT8*)(machine.root_device().memregion("user1")->base() + addr + ((state->m_bank_data[0] >> 1) * 0x20000));
  451      }
  452      else if (addr >= 0x20000 && addr < 0x40000)
  453      {
  454          return (UINT8*)&state->m_video_ram[addr - 0x20000];
  455      }
  456      else
  457      {
  458          return (UINT8*)&state->m_work_ram[addr - 0x40000];
  459      }
  460  }
  461  
  462  
  463  /*
  464      This is based this on the Slipstream technical reference manual.
  465      The Flare One blitter is a simpler design with slightly different parameters
  466      and will require hardware tests to figure everything out correctly.
  467  */
  468  void bfcobra_state::RunBlit(address_space &space)
  469  {
  470  #define BLITPRG_READ(x)     blitter.x = *(blitter_get_addr(space.machine(), blitter.program.addr++))
  471  
  472      struct blitter_t &blitter = m_blitter;
  473      int cycles_used = 0;
  474  
  475  
  476      do
  477      {
  478          UINT8 srcdata = 0;
  479          UINT8 dstdata = 0;
  480  
  481          /* Read the blitter command */
  482          BLITPRG_READ(source.addr0);
  483          BLITPRG_READ(source.addr1);
  484          BLITPRG_READ(source.addr2);
  485          BLITPRG_READ(dest.addr0);
  486          BLITPRG_READ(dest.addr1);
  487          BLITPRG_READ(dest.addr2);
  488          BLITPRG_READ(modectl);
  489          BLITPRG_READ(compfunc);
  490          BLITPRG_READ(outercnt);
  491          BLITPRG_READ(innercnt);
  492          BLITPRG_READ(step);
  493          BLITPRG_READ(pattern);
  494  
  495  #if 0
  496          /* This debug is now wrong ! */
  497          if (DEBUG_BLITTER)
  498          {
  499              mame_printf_debug("\n%s:Blitter: Running command from 0x%.5x\n\n", device->machine().describe_context(), blitter.program.addr - 12);
  500              mame_printf_debug("Command Reg         %.2x",   blitter.command);
  501              mame_printf_debug("     %s %s %s %s %s %s %s\n",
  502                  blitter.command & CMD_RUN ? "RUN" : "     ",
  503                  blitter.command & CMD_COLST ? "COLST" : "     ",
  504                  blitter.command & CMD_PARRD ? "PARRD" : "     ",
  505                  blitter.command & CMD_SRCUP ? "SRCUP" : "     ",
  506                  blitter.command & CMD_DSTUP ? "DSTUP" : "     ");
  507  
  508              mame_printf_debug("Src Address Byte 0  %.2x\n", blitter.source.addr0);
  509              mame_printf_debug("Src Address Byte 1  %.2x\n", blitter.source.addr1);
  510              mame_printf_debug("Src Control         %.2x\n", blitter.source.addr2);
  511              mame_printf_debug("  Src Address       %.5x\n", blitter.source.addr & 0xfffff);
  512              mame_printf_debug("Dest Address Byte 0 %.2x\n", blitter.dest.addr0);
  513              mame_printf_debug("Dest Address Byte 1 %.2x\n", blitter.dest.addr1);
  514              mame_printf_debug("Dest Control        %.2x\n", blitter.dest.addr2);
  515              mame_printf_debug("  Dst. Address      %.5x\n", blitter.dest.addr & 0xfffff);
  516              mame_printf_debug("Mode Control        %.2x",   blitter.modectl);
  517              mame_printf_debug("     %s\n", blitter.modectl & MODE_BITTOBYTE ? "BIT_TO_BYTE" : "");
  518  
  519              mame_printf_debug("Comp. and LFU       %.2x\n", blitter.compfunc);
  520              mame_printf_debug("Outer Loop Count    %.2x (%d)\n", blitter.outercnt, blitter.outercnt);
  521              mame_printf_debug("Inner Loop Count    %.2x (%d)\n", blitter.innercnt, blitter.innercnt);
  522              mame_printf_debug("Step Value          %.2x\n", blitter.step);
  523              mame_printf_debug("Pattern Byte        %.2x\n", blitter.pattern);
  524          }
  525  #endif
  526  
  527          /* Ignore these writes */
  528          if (blitter.dest.addr == 0)
  529              return;
  530  
  531          /* Begin outer loop */
  532          for (;;)
  533          {
  534              UINT8 innercnt = blitter.innercnt;
  535              dstdata = blitter.pattern;
  536  
  537              if (blitter.command & CMD_LINEDRAW)
  538              {
  539                  do
  540                  {
  541                      if (blitter.modectl & MODE_YFRAC)
  542                      {
  543                          if (blitter.modectl & MODE_SSIGN )
  544                              blitter.dest.addr0--;
  545                          else
  546                              blitter.dest.addr0++;
  547                      }
  548                      else
  549                      {
  550                          if (blitter.modectl & MODE_DSIGN )
  551                              blitter.dest.addr1--;
  552                          else
  553                              blitter.dest.addr1++;
  554                      }
  555                      if( blitter.source.addr0 < blitter.step )
  556                      {
  557                          blitter.source.addr0 -=blitter.step ;
  558                          blitter.source.addr0 +=blitter.source.addr1;
  559  
  560                          if ( blitter.modectl & MODE_YFRAC )
  561                          {
  562                              if (blitter.modectl & MODE_DSIGN )
  563                                  blitter.dest.addr1--;
  564                              else
  565                                  blitter.dest.addr1++;
  566                          }
  567                          else
  568                          {
  569                              if (blitter.modectl & MODE_SSIGN )
  570                                  blitter.dest.addr0--;
  571                              else
  572                                  blitter.dest.addr0++;
  573                          }
  574                      }
  575                      else
  576                      {
  577                          blitter.source.addr0 -=blitter.step;
  578                      }
  579  
  580                      *blitter_get_addr(space.machine(), blitter.dest.addr) = blitter.pattern;
  581                      cycles_used++;
  582  
  583                  } while (--innercnt);
  584              }
  585              else do
  586              {
  587                  UINT8   inhibit = 0;
  588  
  589                  /* TODO: Set this correctly */
  590                  UINT8   result = blitter.pattern;
  591  
  592                  if (LOOPTYPE == 3 && innercnt == blitter.innercnt)
  593                  {
  594                      srcdata = *(blitter_get_addr(space.machine(), blitter.source.addr & 0xfffff));
  595                      blitter.source.loword++;
  596                      cycles_used++;
  597                  }
  598  
  599                  /* Enable source address read and increment? */
  600                  if (!(blitter.modectl & (MODE_BITTOBYTE | MODE_PALREMAP)))
  601                  {
  602                      if (LOOPTYPE == 0 || LOOPTYPE == 1)
  603                      {
  604                          srcdata = *(blitter_get_addr(space.machine(), blitter.source.addr & 0xfffff));
  605                          cycles_used++;
  606  
  607                          if (blitter.modectl & MODE_SSIGN)
  608                              blitter.source.loword-- ;
  609                          else
  610                              blitter.source.loword++;
  611  
  612                          result = srcdata;
  613                      }
  614                  }
  615  
  616                  /* Read destination pixel? */
  617                  if (LOOPTYPE == 0)
  618                  {
  619                      dstdata = *blitter_get_addr(space.machine(), blitter.dest.addr & 0xfffff);
  620                      cycles_used++;
  621                  }
  622  
  623                  /* Inhibit depending on the bit selected by the inner count */
  624  
  625                  /* Switch on comparator type? */
  626                  if (blitter.modectl & MODE_BITTOBYTE)
  627                  {
  628                      inhibit = !(srcdata & (1 << (8 - innercnt)));
  629                  }
  630  
  631                  if (blitter.compfunc & CMPFUNC_BEQ)
  632                  {
  633                      if (srcdata == blitter.pattern)
  634                      {
  635                          inhibit = 1;
  636  
  637                          /* TODO: Resume from inhibit? */
  638                          if (blitter.command & CMD_COLST)
  639                              return;
  640                      }
  641                  }
  642                  if (blitter.compfunc & CMPFUNC_LT)
  643                  {
  644                      /* Might be wrong */
  645                      if ((srcdata & 0xc0) < (dstdata & 0xc0))
  646                      {
  647                          inhibit = 1;
  648  
  649                          /* TODO: Resume from inhibit? */
  650                          if (blitter.command & CMD_COLST)
  651                              return;
  652                      }
  653                  }
  654                  if (blitter.compfunc & CMPFUNC_EQ)
  655                  {
  656                      if ((srcdata & 0xc0) == (dstdata & 0xc0))
  657                      {
  658                          inhibit = 1;
  659  
  660                          /* TODO: Resume from inhibit? */
  661                          if (blitter.command & CMD_COLST)
  662                              return;
  663                      }
  664                  }
  665                  if (blitter.compfunc & CMPFUNC_GT)
  666                  {
  667                      /* Might be wrong */
  668                      if ((srcdata & 0xc0) > (dstdata & 0xc0))
  669                      {
  670                          inhibit = 1;
  671  
  672                          /* TODO: Resume from inhibit? */
  673                          if (blitter.command & CMD_COLST)
  674                              return;
  675                      }
  676                  }
  677  
  678                  /* Write the data if not inhibited */
  679                  if (!inhibit)
  680                  {
  681                      if (blitter.modectl == MODE_PALREMAP)
  682                      {
  683                          /*
  684                              In this mode, the source points to a 256 entry lookup table.
  685                              The existing destination pixel is used as a lookup
  686                              into the table and the colours is replaced.
  687                          */
  688                          UINT8 dest = *blitter_get_addr(space.machine(), blitter.dest.addr);
  689                          UINT8 newcol = *(blitter_get_addr(space.machine(), (blitter.source.addr + dest) & 0xfffff));
  690  
  691                          *blitter_get_addr(space.machine(), blitter.dest.addr) = newcol;
  692                          cycles_used += 3;
  693                      }
  694                      else
  695                      {
  696                          UINT8 final_result = 0;
  697  
  698                          if (blitter.compfunc & CMPFUNC_LOG3)
  699                              final_result |= result & dstdata;
  700  
  701                          if (blitter.compfunc & CMPFUNC_LOG2)
  702                              final_result |= result & ~dstdata;
  703  
  704                          if (blitter.compfunc & CMPFUNC_LOG1)
  705                              final_result |= ~result & dstdata;
  706  
  707                          if (blitter.compfunc & CMPFUNC_LOG0)
  708                              final_result |= ~result & ~dstdata;
  709  
  710                          *blitter_get_addr(space.machine(), blitter.dest.addr) = final_result;
  711                          cycles_used++;
  712                      }
  713                  }
  714  
  715                  /* Update destination address */
  716                  if (blitter.modectl & MODE_DSIGN)
  717                      blitter.dest.loword--;
  718                  else
  719                      blitter.dest.loword++;
  720  
  721              } while (--innercnt);
  722  
  723              if (!--blitter.outercnt)
  724              {
  725                  break;
  726              }
  727              else
  728              {
  729                  if (blitter.command & CMD_DSTUP)
  730                      blitter.dest.loword += blitter.step;
  731  
  732                  if (blitter.command & CMD_SRCUP)
  733                      blitter.source.loword += blitter.step;
  734  
  735                  if (blitter.command & CMD_PARRD)
  736                  {
  737                      BLITPRG_READ(innercnt);
  738                      BLITPRG_READ(step);
  739                      BLITPRG_READ(pattern);
  740                  }
  741              }
  742          }
  743  
  744          /* Read next command header */
  745          BLITPRG_READ(command);
  746  
  747      } while (blitter.command  & CMD_RUN);
  748  
  749      /* Burn Z80 cycles while blitter is in operation */
  750      space.device().execute().spin_until_time(attotime::from_nsec( (1000000000 / Z80_XTAL)*cycles_used * 2 ) );
  751  }
  752  
  753  
  754  READ8_MEMBER(bfcobra_state::ramdac_r)
  755  {
  756      struct ramdac_t &ramdac = m_ramdac;
  757      UINT8 val = 0xff;
  758  
  759      switch (offset & 3)
  760      {
  761          case 1:
  762          {
  763              UINT8 *count = &ramdac.count_r;
  764  
  765              if (*count == 0)
  766              {
  767                  rgb_t color;
  768                  color = palette_get_color(machine(), ramdac.addr_r);
  769  
  770                  ramdac.color_r[0] = RGB_RED(color);
  771                  ramdac.color_r[1] = RGB_GREEN(color);
  772                  ramdac.color_r[2] = RGB_BLUE(color);
  773              }
  774  
  775              val = ramdac.color_r[*count];
  776  
  777              /* 8bpp -> 6bpp */
  778              val = ((val & 0xc0) >> 2) | ((val >>2) & 0xf);
  779  
  780              if (++*count == 3)
  781              {
  782                  *count = 0;
  783                  ramdac.addr_r++;
  784              }
  785              break;
  786          }
  787          default:
  788          {
  789              mame_printf_debug("Unhandled RAMDAC read (PC:%.4x)\n", space.device().safe_pcbase());
  790          }
  791      }
  792  
  793      return val;
  794  }
  795  
  796  WRITE8_MEMBER(bfcobra_state::ramdac_w)
  797  {
  798      struct ramdac_t &ramdac = m_ramdac;
  799  
  800      switch (offset & 3)
  801      {
  802          case 0:
  803          {
  804              ramdac.addr_w = data;
  805              break;
  806          }
  807          case 1:
  808          {
  809              data &= 0x3f;
  810              ramdac.color_w[ramdac.count_w] = pal6bit(data);
  811              if (++ramdac.count_w == 3)
  812              {
  813                  palette_set_color_rgb(machine(), ramdac.addr_w, ramdac.color_w[0], ramdac.color_w[1], ramdac.color_w[2]);
  814                  ramdac.count_w = 0;
  815                  ramdac.addr_w++;
  816              }
  817              break;
  818          }
  819          case 2:
  820          {
  821              ramdac.mask = data;
  822              break;
  823          }
  824          case 3:
  825          {
  826              ramdac.addr_r = data;
  827              break;
  828          }
  829      }
  830  }
  831  
  832  /***************************************************************************
  833  
  834      Flare One Register Map
  835  
  836      01  Bank control for Z80 region 0x4000-0x7fff (16kB)    WR
  837      02  Bank control for Z80 region 0x8000-0xbfff (16kB)    WR
  838      03  Bank control for Z80 region 0xc000-0xffff (16kB)    WR
  839  
  840      06  Interrupt status....................................WR
  841      07  Interrupt ack.......................................WR
  842          Writing here sets the line number that vertical interrupt is generated at.
  843          cmd1, bit2 is the 9th bit of the line number
  844          ???? Written with 0x21
  845      08  cmd1                                                WR * bit 6 = screen select
  846          bit2 = 9th bit of vertical interrupt line number
  847          bit6 = 1 = select screen 1 else screen 0
  848      09  cmd2 Linked with c001...............................W * bit 0 = 1 = hires
  849          bit0=1=hi res else lo res (as long as bit7 is 0)
  850          bit5=mask msb of each pixel
  851          bit6=mask 2 msbits of each lores pixel
  852          bit7=1=variable resolution - resolution is set by bit 7 of each vram byte.  bit7=1=2 hires pixels
  853      0A  ???? Written with 0 and 1...........................W
  854          color of border
  855  
  856      0B  Horizontal frame buffer scroll .....................W
  857      0C  Vertical frame buffer scroll .......................W
  858  
  859      0D  Colour hold colour..................................W
  860      0E  Palette value for hi-res magenta....................W
  861      0F  Palette value for hi-res yellow?....................W
  862      14  ....................................................W
  863  
  864      18  Blitter program low byte............................WR
  865      19  Blitter program middle byte.........................W
  866      1A  Blitter program high byte...........................W
  867      1B  Blitter command?....................................W
  868      1C  Blitter status?......................................R
  869      20  Blitter control register............................W
  870  
  871      22  ???? Linked with C002...............................W
  872          Mask of 20
  873  
  874          Joystick: xxx1 11xx                                 R
  875          ? (polled on tight loop):  x1xx xxxx                R
  876  
  877      40: ROM bank select.....................................W
  878  
  879  ***************************************************************************/
  880  
  881  void bfcobra_state::update_irqs()
  882  {
  883      int newstate = m_blitter_irq || m_vblank_irq || m_acia_irq;
  884  
  885      if (newstate != m_irq_state)
  886      {
  887          m_irq_state = newstate;
  888          machine().device("maincpu")->execute().set_input_line(0, m_irq_state ? ASSERT_LINE : CLEAR_LINE);
  889      }
  890  }
  891  
  892  READ8_MEMBER(bfcobra_state::chipset_r)
  893  {
  894      UINT8 val = 0xff;
  895  
  896      switch(offset)
  897      {
  898          case 1:
  899          case 2:
  900          case 3:
  901          {
  902              val = m_bank_data[offset];
  903              break;
  904          }
  905          case 6:
  906          {
  907              /* TODO */
  908              val = m_vblank_irq << 4;
  909              break;
  910          }
  911          case 7:
  912          {
  913              m_vblank_irq = 0;
  914              val = 0x1;
  915  
  916              /* TODO */
  917              update_irqs();
  918              break;
  919          }
  920          case 0x1C:
  921          {
  922              /* Blitter status ? */
  923              val = 0;
  924              break;
  925          }
  926          case 0x20:
  927          {
  928              /* Seems correct - used during RLE pic decoding */
  929              val = m_blitter.dest.addr0;
  930              break;
  931          }
  932          case 0x22:
  933          {
  934              val = 0x40 | ioport("JOYSTICK")->read();
  935              break;
  936          }
  937          default:
  938          {
  939              mame_printf_debug("Flare One unknown read: 0x%.2x (PC:0x%.4x)\n", offset, space.device().safe_pcbase());
  940          }
  941      }
  942  
  943      return val;
  944  }
  945  
  946  WRITE8_MEMBER(bfcobra_state::chipset_w)
  947  {
  948      switch (offset)
  949      {
  950          case 0x01:
  951          case 0x02:
  952          case 0x03:
  953          {
  954              if (data > 0x3f)
  955                  popmessage("%x: Unusual bank access (%x)\n", space.device().safe_pcbase(), data);
  956  
  957              data &= 0x3f;
  958              m_bank_data[offset] = data;
  959              z80_bank(machine(), offset, data);
  960              break;
  961          }
  962  
  963          case 0x08:
  964          {
  965              m_flip_8 = data;
  966              break;
  967          }
  968          case 9:
  969              m_videomode = data;
  970              break;
  971  
  972          case 0x0B:
  973          {
  974              m_h_scroll = data;
  975              break;
  976          }
  977          case 0x0C:
  978          {
  979              m_v_scroll = data;
  980              break;
  981          }
  982          case 0x0E:
  983          {
  984              m_col4bit[5] = data;
  985              m_col3bit[5] = data;
  986              m_col3bit[5 + 8] = data;
  987              break;
  988          }
  989          case 0x0f:
  990          {
  991              m_col4bit[6] = data;
  992              m_col3bit[6] = data;
  993              m_col3bit[6 + 8] = data;
  994              break;
  995          }
  996          case 0x18:
  997          {
  998              m_blitter.program.addr0 = data;
  999              break;
 1000          }
 1001          case 0x19:
 1002          {
 1003              m_blitter.program.addr1 = data;
 1004              break;
 1005          }
 1006          case 0x1A:
 1007          {
 1008              m_blitter.program.addr2 = data;
 1009              break;
 1010          }
 1011          case 0x20:
 1012          {
 1013              m_blitter.command = data;
 1014  
 1015              if (data & CMD_RUN)
 1016                  RunBlit(space);
 1017              else
 1018                  mame_printf_debug("Blitter stopped by IO.\n");
 1019  
 1020              break;
 1021          }
 1022          case 0x22:
 1023          {
 1024              m_flip_22 = data;
 1025              break;
 1026          }
 1027          default:
 1028          {
 1029              mame_printf_debug("Flare One unknown write: 0x%.2x with 0x%.2x (PC:0x%.4x)\n", offset, data, space.device().safe_pcbase());
 1030          }
 1031      }
 1032  }
 1033  
 1034  INLINE void z80_bank(running_machine &machine, int num, int data)
 1035  {
 1036      bfcobra_state *state = machine.driver_data<bfcobra_state>();
 1037      static const char * const bank_names[] = { "bank1", "bank2", "bank3" };
 1038  
 1039      if (data < 0x08)
 1040      {
 1041          UINT32 offset = ((state->m_bank_data[0] >> 1) * 0x20000) + ((0x4000 * data) ^ ((state->m_bank_data[0] & 1) ? 0 : 0x10000));
 1042  
 1043          state->membank(bank_names[num - 1])->set_base(machine.root_device().memregion("user1")->base() + offset);
 1044      }
 1045      else if (data < 0x10)
 1046      {
 1047          state->membank(bank_names[num - 1])->set_base(&state->m_video_ram[(data - 0x08) * 0x4000]);
 1048      }
 1049      else
 1050      {
 1051          state->membank(bank_names[num - 1])->set_base(&state->m_work_ram[(data - 0x10) * 0x4000]);
 1052      }
 1053  }
 1054  
 1055  WRITE8_MEMBER(bfcobra_state::rombank_w)
 1056  {
 1057      m_bank_data[0] = data;
 1058      z80_bank(machine(), 1, m_bank_data[1]);
 1059      z80_bank(machine(), 2, m_bank_data[2]);
 1060      z80_bank(machine(), 3, m_bank_data[3]);
 1061  }
 1062  
 1063  
 1064  
 1065  /***************************************************************************
 1066  
 1067      Split into machine\cobra.c !
 1068  
 1069      Alternatively chuck it all away and borrow the MESS implementation
 1070      because it's a million times better.
 1071  
 1072  ***************************************************************************/
 1073  
 1074  
 1075  /*
 1076      WD37C656C-PL (or equivalent) Floppy Disk Controller
 1077  */
 1078  
 1079  enum fdc_phase
 1080  {
 1081      COMMAND,
 1082      EXECUTION_R,
 1083      EXECUTION_W,
 1084      RESULTS,
 1085  };
 1086  
 1087  enum command
 1088  {
 1089      SENSE_DRIVE_STATUS = 0,
 1090      READ_A_TRACK = 2,
 1091      SPECIFY = 3,
 1092      WRITE_DATA = 5,
 1093      READ_DATA = 6,
 1094      RECALIBRATE = 7,
 1095      SENSE_INTERRUPT_STATUS = 8,
 1096      WRITE_DELETED_DATA = 9,
 1097      READ_ID = 10,
 1098      FORMAT_TRACK = 13,
 1099      READ_DELETED_DATA = 14,
 1100      SEEK = 15,
 1101      SCAN_EQUAL = 17,
 1102      SCAN_LOW_OR_EQUAL = 25,
 1103      SCAN_HIGH_OR_EQUAL = 29
 1104  };
 1105  
 1106  void bfcobra_state::reset_fdc()
 1107  {
 1108      memset(&m_fdc, 0, sizeof(m_fdc));
 1109  
 1110      m_fdc.MSR = 0x80;
 1111      m_fdc.phase = COMMAND;
 1112  }
 1113  
 1114  READ8_MEMBER(bfcobra_state::fdctrl_r)
 1115  {
 1116      UINT8 val = 0;
 1117  
 1118      val = m_fdc.MSR;
 1119  
 1120      return val;
 1121  }
 1122  
 1123  READ8_MEMBER(bfcobra_state::fddata_r)
 1124  {
 1125      struct fdc_t &fdc = m_fdc;
 1126      #define BPS     1024
 1127      #define SPT     10
 1128      #define BPT     1024*10
 1129  
 1130      UINT8 val = 0;
 1131  
 1132      if (fdc.phase == EXECUTION_R)
 1133      {
 1134          switch (fdc.cmd[0] & 0x1f)
 1135          {
 1136              /* Specify */
 1137              case READ_DATA:
 1138              {
 1139                  if (fdc.setup_read)
 1140                  {
 1141                      fdc.track = fdc.cmd[2];
 1142                      fdc.side = fdc.cmd[3];
 1143                      fdc.sector = fdc.cmd[4];
 1144                      fdc.number = fdc.cmd[5];
 1145                      fdc.stop_track = fdc.cmd[6];
 1146                      //int GPL = fdc.cmd[7];
 1147                      //int DTL = fdc.cmd[8];
 1148  
 1149                      fdc.setup_read = 0;
 1150                      fdc.byte_pos = 0;
 1151                  }
 1152  
 1153                  fdc.offset = (BPT * fdc.track*2) + (fdc.side ? BPT : 0) + (BPS * (fdc.sector-1)) + fdc.byte_pos++;
 1154                  val = *(machine().root_device().memregion("user2")->base() + fdc.offset);
 1155  
 1156                  /* Move on to next sector? */
 1157                  if (fdc.byte_pos == 1024)
 1158                  {
 1159                      fdc.byte_pos = 0;
 1160  
 1161                      if (fdc.sector == fdc.stop_track || ++fdc.sector == 11)
 1162                      {
 1163                          /* End of read operation */
 1164                          fdc.MSR = 0xd0;
 1165                          fdc.phase = RESULTS;
 1166  
 1167                          fdc.results[0] = 0;
 1168                          fdc.results[1] = 0;
 1169                          fdc.results[2] = 0;
 1170  
 1171                          fdc.results[3] = 0;
 1172                          fdc.results[4] = 0;
 1173                          fdc.results[5] = 0;
 1174                          fdc.results[6] = 0;
 1175                      }
 1176                  }
 1177                  break;
 1178              }
 1179          }
 1180      }
 1181      else if (fdc.phase == RESULTS)
 1182      {
 1183          val = fdc.results[fdc.res_cnt++];
 1184  
 1185          if (fdc.res_cnt == fdc.res_len)
 1186          {
 1187              fdc.phase = COMMAND;
 1188              fdc.res_cnt = 0;
 1189              fdc.MSR &= ~0x40;
 1190          }
 1191      }
 1192  
 1193      return val;
 1194  }
 1195  
 1196  WRITE8_MEMBER(bfcobra_state::fdctrl_w)
 1197  {
 1198      struct fdc_t &fdc = m_fdc;
 1199      switch (fdc.phase)
 1200      {
 1201          case COMMAND:
 1202          {
 1203              command_phase(fdc, data);
 1204              break;
 1205          }
 1206          case EXECUTION_W:
 1207          {
 1208              exec_w_phase(data);
 1209              break;
 1210          }
 1211          default:
 1212          {
 1213              mame_printf_debug("Unknown FDC phase?!");
 1214          }
 1215      }
 1216  }
 1217  
 1218  void bfcobra_state::command_phase(struct fdc_t &fdc, UINT8 data)
 1219  {
 1220      if (fdc.cmd_cnt == 0)
 1221      {
 1222          fdc.cmd[0] = data;
 1223  
 1224          fdc.cmd_cnt = 1;
 1225  
 1226          switch (data & 0x1f)
 1227          {
 1228              /* Specify */
 1229              case READ_DATA:
 1230              {
 1231  //              mame_printf_debug("Read data\n");
 1232                  fdc.cmd_len = 9;
 1233                  fdc.res_len = 7;
 1234                  fdc.next_phase = EXECUTION_R;
 1235                  fdc.setup_read = 1;
 1236                  break;
 1237              }
 1238              case SPECIFY:
 1239              {
 1240  //              mame_printf_debug("Specify\n");
 1241                  fdc.cmd_len = 3;
 1242                  fdc.res_len = 0;
 1243                  fdc.next_phase = COMMAND;
 1244                  break;
 1245              }
 1246              case RECALIBRATE:
 1247              {
 1248  //              mame_printf_debug("Recalibrate\n");
 1249                  fdc.cmd_len = 2;
 1250                  fdc.res_len = 0;
 1251                  fdc.next_phase = COMMAND;
 1252                  //fdc.MSR |= 0x40;
 1253                  break;
 1254              }
 1255              case SENSE_INTERRUPT_STATUS:
 1256              {
 1257  //              mame_printf_debug("Sense interrupt status\n");
 1258                  fdc.cmd_len = 1;
 1259                  fdc.res_len = 2;
 1260                  fdc.phase = RESULTS;
 1261  
 1262                  fdc.results[0] = 0;
 1263                  fdc.results[1] = 0;
 1264  
 1265                  fdc.cmd_cnt = 0;
 1266                  fdc.MSR |= 0x40;
 1267                  break;
 1268              }
 1269              case SEEK:
 1270              {
 1271  //              mame_printf_debug("Seek\n");
 1272                  fdc.cmd_len = 3;
 1273                  fdc.res_len = 0;
 1274                  fdc.next_phase = COMMAND;
 1275                  break;
 1276              }
 1277              default:
 1278              {
 1279  //              mame_printf_debug("%x\n",data & 0x1f);
 1280              }
 1281          }
 1282      }
 1283      else
 1284      {
 1285          fdc.cmd[fdc.cmd_cnt++] = data;
 1286          //mame_printf_debug(" %x\n",data);
 1287      }
 1288  
 1289      if (fdc.cmd_cnt == fdc.cmd_len)
 1290      {
 1291          fdc.phase = fdc.next_phase;
 1292          fdc.cmd_cnt = 0;
 1293  
 1294          if ((fdc.cmd[0] & 0x1f) == READ_DATA)
 1295              fdc.MSR = 0xf0;
 1296      }
 1297  }
 1298  
 1299  #ifdef UNUSED_FUNCTION
 1300  UINT8 exec_r_phase(void)
 1301  {
 1302      return 0;
 1303  }
 1304  #endif
 1305  
 1306  void bfcobra_state::exec_w_phase(UINT8 data)
 1307  {
 1308  }
 1309  
 1310  #ifdef UNUSED_FUNCTION
 1311  UINT8 results_phase(void)
 1312  {
 1313      return 0;
 1314  }
 1315  
 1316  WRITE8_MEMBER(bfcobra_state::fd_op_w)
 1317  {
 1318  }
 1319  
 1320  WRITE8_MEMBER(bfcobra_state::fd_ctrl_w)
 1321  {
 1322  }
 1323  #endif
 1324  
 1325  void bfcobra_state::machine_reset()
 1326  {
 1327      unsigned int pal;
 1328  
 1329      for (pal = 0; pal < 256; ++pal)
 1330      {
 1331          palette_set_color_rgb(machine(), pal, pal3bit((pal>>5)&7), pal3bit((pal>>2)&7), pal2bit(pal&3));
 1332      }
 1333  
 1334      m_bank_data[0] = 1;
 1335      memset(&m_ramdac, 0, sizeof(m_ramdac));
 1336      reset_fdc();
 1337  
 1338      m_irq_state = m_blitter_irq = m_vblank_irq = m_acia_irq = 0;
 1339  }
 1340  
 1341  /***************************************************************************
 1342  
 1343      Cobra I/Viper Z80 Memory Map
 1344  
 1345  ***************************************************************************/
 1346  
 1347  static ADDRESS_MAP_START( z80_prog_map, AS_PROGRAM, 8, bfcobra_state )
 1348      AM_RANGE(0x0000, 0x3fff) AM_ROMBANK("bank4")
 1349      AM_RANGE(0x4000, 0x7fff) AM_RAMBANK("bank1")
 1350      AM_RANGE(0x8000, 0xbfff) AM_RAMBANK("bank2")
 1351      AM_RANGE(0xc000, 0xffff) AM_RAMBANK("bank3")
 1352  ADDRESS_MAP_END
 1353  
 1354  static ADDRESS_MAP_START( z80_io_map, AS_IO, 8, bfcobra_state )
 1355  ADDRESS_MAP_GLOBAL_MASK(0xff)
 1356      AM_RANGE(0x00, 0x23) AM_READWRITE(chipset_r, chipset_w)
 1357      AM_RANGE(0x24, 0x24) AM_DEVWRITE("acia6850_0", acia6850_device, control_write)
 1358      AM_RANGE(0x25, 0x25) AM_DEVWRITE("acia6850_0", acia6850_device, data_write)
 1359      AM_RANGE(0x26, 0x26) AM_DEVREAD("acia6850_0", acia6850_device, status_read)
 1360      AM_RANGE(0x27, 0x27) AM_DEVREAD("acia6850_0", acia6850_device, data_read)
 1361      AM_RANGE(0x30, 0x30) AM_READ(fdctrl_r)
 1362      AM_RANGE(0x31, 0x31) AM_READWRITE(fddata_r, fdctrl_w)
 1363      AM_RANGE(0x40, 0x40) AM_WRITE(rombank_w)
 1364      AM_RANGE(0x50, 0x53) AM_READWRITE(ramdac_r, ramdac_w)
 1365  ADDRESS_MAP_END
 1366  
 1367  
 1368  /***************************************************************************
 1369  
 1370      Cobra I/Viper 6809 Memory Map
 1371  
 1372      Cobra I has these components:
 1373  
 1374      EF68B50P            - For communication with Z80
 1375      EF68B50P            - For data retrieval
 1376      AY38912A
 1377      UPD7759C
 1378      BFM1090 (CF30056)   - 'TEXAS' I/O chip, lamps and misc
 1379      BFM1095 (CF30057)   - 'TEXAS' I/O chip, handles switches
 1380      BFM1071             - 6809 Address decoding and bus control
 1381  
 1382      /IRQ provided by EF68850P at IC38
 1383      /FIRQ connected to meter current sensing circuitry
 1384  
 1385      TODO: Calculate watchdog timer period.
 1386  
 1387  ***************************************************************************/
 1388  
 1389  /* TODO */
 1390  READ8_MEMBER(bfcobra_state::int_latch_r)
 1391  {
 1392      return 2 | 1;
 1393  }
 1394  
 1395  /* TODO */
 1396  READ8_MEMBER(bfcobra_state::meter_r)
 1397  {
 1398      return m_meter_latch;
 1399  }
 1400  
 1401  /* TODO: This is borrowed from Scorpion 1 */
 1402  WRITE8_MEMBER(bfcobra_state::meter_w)
 1403  {
 1404      int i;
 1405      int  changed = m_meter_latch ^ data;
 1406  
 1407      m_meter_latch = data;
 1408  
 1409      /*
 1410          When a meter is triggered, the current drawn is sensed. If a meter
 1411          is connected, the /FIRQ line will be pulsed.
 1412      */
 1413      for (i = 0; i < 8; i++)
 1414      {
 1415          if (changed & (1 << i))
 1416          {
 1417              MechMtr_update(i, data & (1 << i) );
 1418              generic_pulse_irq_line(space.device().execute(), M6809_FIRQ_LINE, 1);
 1419          }
 1420      }
 1421  }
 1422  
 1423  /* TODO */
 1424  READ8_MEMBER(bfcobra_state::latch_r)
 1425  {
 1426      return m_mux_input;
 1427  }
 1428  
 1429  WRITE8_MEMBER(bfcobra_state::latch_w)
 1430  {
 1431      /* TODO: This is borrowed from Scorpion 1 */
 1432      switch(offset)
 1433      {
 1434          case 0:
 1435          {
 1436              int changed = m_mux_outputlatch ^ data;
 1437              static const char *const port[] = { "STROBE0", "STROBE1", "STROBE2", "STROBE3", "STROBE4", "STROBE5", "STROBE6", "STROBE7" };
 1438  
 1439              m_mux_outputlatch = data;
 1440  
 1441              /* Clock has changed */
 1442              if (changed & 0x08)
 1443              {
 1444                  int input_strobe = data & 0x7;
 1445  
 1446                  /* Clock is low */
 1447                  if (!(data & 0x08))
 1448                      m_mux_input = ioport(port[input_strobe])->read();
 1449              }
 1450              break;
 1451          }
 1452          case 1:
 1453          {
 1454  //          strobe_data_l = data;
 1455              break;
 1456          }
 1457          case 2:
 1458          {
 1459  //          strobe_data_h = data;
 1460              break;
 1461          }
 1462      }
 1463  }
 1464  
 1465  READ8_MEMBER(bfcobra_state::upd_r)
 1466  {
 1467      device_t *device = machine().device("upd");
 1468      return 2 | upd7759_busy_r(device);
 1469  }
 1470  
 1471  WRITE8_MEMBER(bfcobra_state::upd_w)
 1472  {
 1473      device_t *device = machine().device("upd");
 1474      upd7759_reset_w(device, data & 0x80);
 1475      upd7759_port_w(device, space, 0, data & 0x3f);
 1476      upd7759_start_w(device, data & 0x40 ? 0 : 1);
 1477  }
 1478  
 1479  static ADDRESS_MAP_START( m6809_prog_map, AS_PROGRAM, 8, bfcobra_state )
 1480      AM_RANGE(0x0000, 0x1fff) AM_RAM AM_SHARE("nvram")
 1481      AM_RANGE(0x2000, 0x2000) AM_RAM     // W 'B', 6F
 1482      AM_RANGE(0x2200, 0x2200) AM_RAM     // W 'F'
 1483      AM_RANGE(0x2600, 0x2600) AM_READWRITE(meter_r, meter_w)
 1484      AM_RANGE(0x2800, 0x2800) AM_RAM     // W
 1485      AM_RANGE(0x2A00, 0x2A02) AM_READWRITE(latch_r, latch_w)
 1486      AM_RANGE(0x2E00, 0x2E00) AM_READ(int_latch_r)
 1487      AM_RANGE(0x3001, 0x3001) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_w)
 1488      AM_RANGE(0x3201, 0x3201) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w)
 1489      AM_RANGE(0x3404, 0x3404) AM_DEVREADWRITE("acia6850_1", acia6850_device, status_read, control_write)
 1490      AM_RANGE(0x3405, 0x3405) AM_DEVREADWRITE("acia6850_1", acia6850_device, data_read, data_write)
 1491      AM_RANGE(0x3406, 0x3406) AM_DEVREADWRITE("acia6850_2", acia6850_device, status_read, control_write)
 1492      AM_RANGE(0x3407, 0x3407) AM_DEVREADWRITE("acia6850_2", acia6850_device, data_read, data_write)
 1493  //  AM_RANGE(0x3408, 0x3408) AM_NOP
 1494  //  AM_RANGE(0x340A, 0x340A) AM_NOP
 1495  //  AM_RANGE(0x3600, 0x3600) AM_NOP
 1496      AM_RANGE(0x3801, 0x3801) AM_READWRITE(upd_r, upd_w)
 1497      AM_RANGE(0x8000, 0xffff) AM_ROM
 1498      AM_RANGE(0xf000, 0xf000) AM_WRITENOP    /* Watchdog */
 1499  ADDRESS_MAP_END
 1500  
 1501  static INPUT_PORTS_START( bfcobra )
 1502      PORT_START("STROBE0")
 1503      PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_NAME("Coin: 10p")
 1504      PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 ) PORT_NAME("Coin: 20p")
 1505      PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_COIN3 ) PORT_NAME("Coin: 50p")
 1506      PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_COIN4 ) PORT_NAME("Coin: 1 pound")
 1507      PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNKNOWN )
 1508      PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SERVICE ) PORT_NAME("Green Test?") PORT_CODE(KEYCODE_F1)
 1509      PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SERVICE ) PORT_NAME("Red Test?")
 1510      PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
 1511  
 1512      PORT_START("STROBE1")
 1513      PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Pass") PORT_CODE(KEYCODE_A)
 1514      PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Continue") PORT_CODE(KEYCODE_S)
 1515      PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Collect") PORT_CODE(KEYCODE_D)
 1516      PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_START1 ) PORT_NAME("Start")
 1517      PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Bonus") PORT_CODE(KEYCODE_F)
 1518  //  PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON1 )
 1519  //  PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON2 )
 1520  //  PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON3 )
 1521  
 1522      PORT_START("STROBE2")
 1523      PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON5 ) PORT_NAME("<A")
 1524      PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON6 ) PORT_NAME("<B")
 1525      PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON7 ) PORT_NAME("<C")
 1526      PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_BUTTON8 ) PORT_NAME("A>")
 1527      PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON9 ) PORT_NAME("B>")
 1528      PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON10 ) PORT_NAME("C>")
 1529      PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
 1530      PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
 1531  
 1532      PORT_START("STROBE3")
 1533      PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_INTERLOCK) PORT_NAME("Cash box door") PORT_CODE(KEYCODE_Y) PORT_TOGGLE
 1534      PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_SERVICE ) PORT_NAME("Front Door? (resets)") PORT_CODE(KEYCODE_T) PORT_TOGGLE
 1535      PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_SERVICE ) PORT_NAME("Refill Key") PORT_CODE(KEYCODE_R) PORT_TOGGLE
 1536      PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNKNOWN )
 1537      PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNKNOWN )
 1538      PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
 1539      PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
 1540      PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
 1541  
 1542      PORT_START("STROBE4")
 1543      PORT_BIT( 0xFF, IP_ACTIVE_HIGH, IPT_UNKNOWN )
 1544  
 1545      PORT_START("STROBE5")
 1546      PORT_BIT( 0xFF, IP_ACTIVE_HIGH, IPT_UNKNOWN )
 1547  
 1548      PORT_START("STROBE6")
 1549      PORT_DIPNAME( 0x01, 0x00, "DIL09" )
 1550      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
 1551      PORT_DIPSETTING(    0x01, DEF_STR( On  ) )
 1552      PORT_DIPNAME( 0x02, 0x00, "DIL10" )
 1553      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
 1554      PORT_DIPSETTING(    0x02, DEF_STR( On  ) )
 1555      PORT_DIPNAME( 0x04, 0x00, "DIL11" )
 1556      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
 1557      PORT_DIPSETTING(    0x04, DEF_STR( On  ) )
 1558      PORT_DIPNAME( 0x08, 0x00, "DIL12" )
 1559      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
 1560      PORT_DIPSETTING(    0x08, DEF_STR( On  ) )
 1561      PORT_DIPNAME( 0x10, 0x00, "DIL13" )
 1562      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
 1563      PORT_DIPSETTING(    0x10, DEF_STR( On  ) )
 1564      PORT_DIPNAME( 0x20, 0x00, "DIL14" )
 1565      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
 1566      PORT_DIPSETTING(    0x20, DEF_STR( On  ) )
 1567      PORT_DIPNAME( 0x40, 0x00, "DIL15" )
 1568      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
 1569      PORT_DIPSETTING(    0x40, DEF_STR( On  ) )
 1570      PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
 1571  
 1572      PORT_START("STROBE7")
 1573      PORT_DIPNAME( 0x01, 0x00, "DIL02" )
 1574      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
 1575      PORT_DIPSETTING(    0x01, DEF_STR( On  ) )
 1576      PORT_DIPNAME( 0x02, 0x00, "DIL03" )
 1577      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
 1578      PORT_DIPSETTING(    0x02, DEF_STR( On  ) )
 1579      PORT_DIPNAME( 0x04, 0x00, "DIL04" )
 1580      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
 1581      PORT_DIPSETTING(    0x04, DEF_STR( On  ) )
 1582      PORT_DIPNAME( 0x08, 0x00, "DIL05" )
 1583      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
 1584      PORT_DIPSETTING(    0x08, DEF_STR( On  ) )
 1585      PORT_DIPNAME( 0x10, 0x00, "DIL06" )
 1586      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
 1587      PORT_DIPSETTING(    0x10, DEF_STR( On  ) )
 1588      PORT_DIPNAME( 0x20, 0x00, "DIL07" )
 1589      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
 1590      PORT_DIPSETTING(    0x20, DEF_STR( On  ) )
 1591      PORT_DIPNAME( 0x40, 0x00, "DIL08" )
 1592      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
 1593      PORT_DIPSETTING(    0x40, DEF_STR( On  ) )
 1594      PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
 1595  
 1596      PORT_START("JOYSTICK")
 1597      PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP )
 1598      PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN )
 1599      PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT )
 1600      PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT )
 1601      PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 )
 1602  INPUT_PORTS_END
 1603  
 1604  /*
 1605      Allocate work RAM and video RAM shared by the Z80 and chipset.
 1606  */
 1607  void bfcobra_state::init_ram()
 1608  {
 1609      /* 768kB work RAM */
 1610      m_work_ram = auto_alloc_array_clear(machine(), UINT8, 0xC0000);
 1611  
 1612      /* 128kB video RAM */
 1613      m_video_ram = auto_alloc_array_clear(machine(), UINT8, 0x20000);
 1614  }
 1615  
 1616  /*
 1617      What are the correct ACIA clocks ?
 1618  */
 1619  
 1620  READ_LINE_MEMBER(bfcobra_state::z80_acia_rx_r)
 1621  {
 1622      return m_m6809_z80_line;
 1623  }
 1624  
 1625  WRITE_LINE_MEMBER(bfcobra_state::z80_acia_tx_w)
 1626  {
 1627      m_z80_m6809_line = state;
 1628  }
 1629  
 1630  WRITE_LINE_MEMBER(bfcobra_state::z80_acia_irq)
 1631  {
 1632      m_acia_irq = state;
 1633      update_irqs();
 1634  }
 1635  
 1636  static ACIA6850_INTERFACE( z80_acia_if )
 1637  {
 1638      500000,
 1639      500000,
 1640      DEVCB_DRIVER_LINE_MEMBER(bfcobra_state,z80_acia_rx_r), /*&m6809_z80_line,*/
 1641      DEVCB_DRIVER_LINE_MEMBER(bfcobra_state,z80_acia_tx_w), /*&z80_m6809_line,*/
 1642      DEVCB_NULL,
 1643      DEVCB_NULL,
 1644      DEVCB_NULL,
 1645      DEVCB_DRIVER_LINE_MEMBER(bfcobra_state,z80_acia_irq)
 1646  };
 1647  
 1648  READ_LINE_MEMBER(bfcobra_state::m6809_acia_rx_r)
 1649  {
 1650      return m_z80_m6809_line;
 1651  }
 1652  
 1653  WRITE_LINE_MEMBER(bfcobra_state::m6809_acia_tx_w)
 1654  {
 1655      m_m6809_z80_line = state;
 1656  }
 1657  
 1658  WRITE_LINE_MEMBER(bfcobra_state::m6809_data_irq)
 1659  {
 1660      machine().device("audiocpu")->execute().set_input_line(M6809_IRQ_LINE, state ? CLEAR_LINE : ASSERT_LINE);
 1661  }
 1662  
 1663  static ACIA6850_INTERFACE( m6809_acia_if )
 1664  {
 1665      500000,
 1666      500000,
 1667      DEVCB_DRIVER_LINE_MEMBER(bfcobra_state,m6809_acia_rx_r),/*&z80_m6809_line,*/
 1668      DEVCB_DRIVER_LINE_MEMBER(bfcobra_state,m6809_acia_tx_w),/*&m6809_z80_line,*/
 1669      DEVCB_NULL,
 1670      DEVCB_NULL,
 1671      DEVCB_NULL,
 1672      DEVCB_NULL
 1673  };
 1674  
 1675  READ_LINE_MEMBER(bfcobra_state::data_acia_rx_r)
 1676  {
 1677      return m_data_r;
 1678  }
 1679  
 1680  WRITE_LINE_MEMBER(bfcobra_state::data_acia_tx_w)
 1681  {
 1682          m_data_t = state;
 1683  }
 1684  
 1685  
 1686  static ACIA6850_INTERFACE( data_acia_if )
 1687  {
 1688      500000,
 1689      500000,
 1690      DEVCB_DRIVER_LINE_MEMBER(bfcobra_state,data_acia_rx_r),/*data_r,*/
 1691      DEVCB_DRIVER_LINE_MEMBER(bfcobra_state,data_acia_tx_w),/*data_t,*/
 1692      DEVCB_NULL,
 1693      DEVCB_NULL,
 1694      DEVCB_NULL,
 1695      DEVCB_DRIVER_LINE_MEMBER(bfcobra_state,m6809_data_irq)
 1696  };
 1697  
 1698  
 1699  /* TODO: Driver vs Machine Init */
 1700  DRIVER_INIT_MEMBER(bfcobra_state,bfcobra)
 1701  {
 1702      /*
 1703          6809 ROM address and data lines are scrambled.
 1704          This is the same scrambling as Scorpion 2.
 1705      */
 1706      static const UINT8 datalookup[] = { 1, 3, 5, 6, 4, 2, 0, 7 };
 1707      static const UINT8 addrlookup[] = { 11, 12, 0, 2, 3, 5, 7, 9, 8, 6, 1, 4, 10, 13, 14 };
 1708  
 1709      UINT32 i;
 1710      UINT8 *rom;
 1711      UINT8 *tmp;
 1712  
 1713      tmp = auto_alloc_array(machine(), UINT8, 0x8000);
 1714      rom = machine().root_device().memregion("audiocpu")->base() + 0x8000;
 1715      memcpy(tmp, rom, 0x8000);
 1716  
 1717      for (i = 0; i < 0x8000; i++)
 1718      {
 1719          UINT16 addr = 0;
 1720          UINT8 x;
 1721          UINT8 data = 0;
 1722          UINT8 val = tmp[i];
 1723  
 1724          for (x = 0; x < 8; x ++)
 1725              data |= ((val >> x) & 1) << datalookup[x];
 1726  
 1727          for (x = 0; x < 15; x ++)
 1728              addr |= ((i >> x) & 1)  << addrlookup[x];
 1729  
 1730          rom[addr] = data;
 1731      }
 1732  
 1733      auto_free(machine(), tmp);
 1734  
 1735      init_ram();
 1736  
 1737      m_bank_data[0] = 1;
 1738      m_bank_data[1] = 0;
 1739      m_bank_data[2] = 0;
 1740      m_bank_data[3] = 0;
 1741  
 1742      /* Fixed 16kB ROM region */
 1743      membank("bank4")->set_base(machine().root_device().memregion("user1")->base());
 1744  
 1745      /* TODO: Properly sort out the data ACIA */
 1746      m_data_r = 1;
 1747  
 1748      /* Finish this */
 1749      state_save_register_global(machine(), m_z80_m6809_line);
 1750      state_save_register_global(machine(), m_m6809_z80_line);
 1751      state_save_register_global(machine(), m_data_r);
 1752      state_save_register_global(machine(), m_data_t);
 1753      state_save_register_global(machine(), m_h_scroll);
 1754      state_save_register_global(machine(), m_v_scroll);
 1755      state_save_register_global(machine(), m_flip_8);
 1756      state_save_register_global(machine(), m_flip_22);
 1757      state_save_register_global(machine(), m_z80_int);
 1758      state_save_register_global(machine(), m_z80_inten);
 1759      state_save_register_global_array(machine(), m_bank_data);
 1760      state_save_register_global_pointer(machine(), m_work_ram, 0xc0000);
 1761      state_save_register_global_pointer(machine(), m_video_ram, 0x20000);
 1762  }
 1763  
 1764  /* TODO */
 1765  INTERRUPT_GEN_MEMBER(bfcobra_state::timer_irq)
 1766  {
 1767      generic_pulse_irq_line(device.execute(), M6809_IRQ_LINE, 1);
 1768  }
 1769  
 1770  /* TODO */
 1771  INTERRUPT_GEN_MEMBER(bfcobra_state::vblank_gen)
 1772  {
 1773      m_vblank_irq = 1;
 1774      update_irqs();
 1775  }
 1776  
 1777  static MACHINE_CONFIG_START( bfcobra, bfcobra_state )
 1778      MCFG_CPU_ADD("maincpu", Z80, Z80_XTAL)
 1779      MCFG_CPU_PROGRAM_MAP(z80_prog_map)
 1780      MCFG_CPU_IO_MAP(z80_io_map)
 1781      MCFG_CPU_VBLANK_INT_DRIVER("screen", bfcobra_state,  vblank_gen)
 1782  
 1783      MCFG_CPU_ADD("audiocpu", M6809, M6809_XTAL)
 1784      MCFG_CPU_PROGRAM_MAP(m6809_prog_map)
 1785      MCFG_CPU_PERIODIC_INT_DRIVER(bfcobra_state, timer_irq,  1000)
 1786  
 1787      MCFG_NVRAM_ADD_0FILL("nvram")
 1788  
 1789  
 1790      /* TODO */
 1791      MCFG_SCREEN_ADD("screen", RASTER)
 1792      MCFG_SCREEN_REFRESH_RATE(50)
 1793      MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
 1794      MCFG_SCREEN_SIZE(512, 256)
 1795      MCFG_SCREEN_VISIBLE_AREA(0, 512 - 1, 0, 256 - 1)
 1796      MCFG_SCREEN_UPDATE_DRIVER(bfcobra_state, screen_update_bfcobra)
 1797  
 1798      MCFG_PALETTE_LENGTH(256)
 1799  
 1800      MCFG_SPEAKER_STANDARD_MONO("mono")
 1801  
 1802      MCFG_SOUND_ADD("aysnd", AY8910, M6809_XTAL)
 1803      MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.20)
 1804  
 1805      MCFG_SOUND_ADD("upd", UPD7759, UPD7759_STANDARD_CLOCK)
 1806      MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.40)
 1807  
 1808  
 1809      /* ACIAs */
 1810      MCFG_ACIA6850_ADD("acia6850_0", z80_acia_if)
 1811      MCFG_ACIA6850_ADD("acia6850_1", m6809_acia_if)
 1812      MCFG_ACIA6850_ADD("acia6850_2", data_acia_if)
 1813  MACHINE_CONFIG_END
 1814  
 1815  /***************************************************************************
 1816  
 1817    Game driver(s)
 1818  
 1819    Note: Two different versions of each 6809 ROM exist: standard and protocol
 1820    It appears sets can be a combination of disk images, 6809 and Z80 ROMs!
 1821  
 1822  ***************************************************************************/
 1823  
 1824  ROM_START( inquiztr )
 1825      ROM_REGION( 0x10000, "audiocpu", 0 )
 1826      ROM_LOAD( "inq6809", 0x08000, 0x08000, CRC(ae996600) SHA1(f360399e77b81399d910770fa8106c196f04363c) )
 1827  
 1828      ROM_REGION( 0x20000, "user1", 0 )
 1829      ROM_LOAD( "9576002.bin", 0x00000, 0x10000, CRC(5b8c8a04) SHA1(af5328fee79c370f45bff36f534aaf50964b6900) )
 1830  
 1831      ROM_REGION( 0x20000, "altuser1", 0 )
 1832      ROM_LOAD( "9576028.bin", 0x10000, 0x10000, CRC(2d85682c) SHA1(baec47bff4b8beef5afbb737dc57b22bf93ebcf8) )
 1833  
 1834          // these look quite different.. (like they belong together) but booting with these gives a checksum error (banking?)
 1835      ROM_LOAD( "inqvypp1", 0x00000, 0x010000, CRC(9bac8c6e) SHA1(15e24d60c2f3997e637694f60daa552b22628766) )
 1836      ROM_LOAD( "inqvypp2", 0x10000, 0x010000, CRC(f9cd196c) SHA1(0ac31d87462cbee6f41e19aefe740d876910bdf5) )
 1837  
 1838      ROM_REGION( 0x1c2000, "user2", 0 )
 1839      ROM_LOAD( "inqdisk.img", 0x000000, 0x1c2000, NO_DUMP )
 1840  ROM_END
 1841  
 1842  
 1843  
 1844  
 1845  ROM_START( escounts )
 1846      ROM_REGION( 0x10000, "audiocpu", 0 )
 1847      ROM_LOAD( "esc12int", 0x08000, 0x08000, CRC(741a1fe6) SHA1(e741d0ae0d2f11036a358120381e4b0df4a560a1) )
 1848  
 1849      ROM_REGION( 0x10000, "altrevs", 0 )
 1850      ROM_LOAD( "bfm_esc.bin", 0x08000, 0x08000, CRC(27acb5a5) SHA1(da50d650ab6456d61d0fb7f89247f2040b4bb9a8) )
 1851      ROM_LOAD( "escint1b",    0x08000, 0x08000, CRC(fde413c9) SHA1(18724a1b771ba4c72e571c356591c5be32948d7a) )
 1852  
 1853      ROM_REGION( 0x10000, "user1", 0 )
 1854      ROM_LOAD( "esccobpa", 0x00000, 0x10000, CRC(d8eadeb7) SHA1(9b94f1454e6a17bf8321b0ef4ddd0ed1a56150f7) )
 1855  
 1856      /* 95-100-207 */
 1857      ROM_REGION( 0x190000, "user2", 0 )
 1858      ROM_LOAD( "escdisk4.img", 0x000000, 0x190000, CRC(24156e0f) SHA1(e163daa8effadd93ace2bc2ba1af0f4a190abd7f) )
 1859  ROM_END
 1860  
 1861  ROM_START( trebltop )
 1862      ROM_REGION( 0x10000, "audiocpu", 0 )
 1863      ROM_LOAD( "95740078.bin", 0x08000, 0x08000, CRC(aca1980b) SHA1(3d4ed1dc545cc80f56d7daa13028fb10a12a718b) )
 1864  
 1865      ROM_REGION( 0x10000, "altrevs", 0 )
 1866      ROM_LOAD( "ttopint", 0x08000, 0x08000, CRC(cc798f90) SHA1(c3f541ebbb3a2c29cc4f00bbd47e289bcff50ecb) )
 1867  
 1868      ROM_REGION( 0x20000, "user1", 0 )
 1869      ROM_LOAD( "95760031.bin", 0x00000, 0x10000, CRC(8e75edb8) SHA1(0aaa3834d5ac20f92bdf1f2b8f1eb71854469cbe) )
 1870      ROM_LOAD( "95760021.bin", 0x10000, 0x10000, CRC(f42016c0) SHA1(7067d018cb4bdcfba777267fb01cddf44e4216c3) )
 1871  
 1872      ROM_REGION( 0x1c2000, "user2", 0 )
 1873      ROM_LOAD( "ttdisk1.img", 0x000000, 0x190000, CRC(b2003228) SHA1(5eb49f05137cdd404f22948d39aa79c1518c06eb) )
 1874  
 1875      ROM_REGION( 0x20000, "upd", 0 )
 1876      ROM_LOAD( "95000172.bin", 0x00000, 0x10000, CRC(e85367a5) SHA1(695fd95ddeecdb16602f7b0f075cf5128a2fb808) )
 1877      ROM_LOAD( "95000173.bin", 0x10000, 0x10000, CRC(8bda2c5e) SHA1(79aab5a2af7a5add5fe9132dc13bcc3705c6faf3) )
 1878  ROM_END
 1879  
 1880  ROM_START( beeline )
 1881      ROM_REGION( 0x10000, "audiocpu", 0 )
 1882      ROM_LOAD( "bln12int.a", 0x08000, 0x08000, CRC(cb97905e) SHA1(9725156bf64e53a56bc0f90795d4b07db41d059e) )
 1883  
 1884      ROM_REGION( 0x10000, "altrevs", 0 )
 1885      ROM_LOAD( "beeint12", 0x8000, 0x008000, CRC(0a77d0be) SHA1(8e55e7b4eb85cc2521d8fdf7ede02131ed80372e) )
 1886  
 1887  
 1888      ROM_REGION( 0x20000, "user1", 0 )
 1889      ROM_LOAD( "blncob.pa", 0x00000, 0x10000, CRC(8abc0017) SHA1(ecf6e7a4021b35295eb9bb9aed1b88fff27ffbd1) )
 1890      ROM_LOAD( "blncob.pb", 0x10000, 0x10000, CRC(feb121fe) SHA1(e83bfd6db00a3264e5076f257e261a1cb4605a83) )
 1891  
 1892      ROM_REGION( 0x1c2000, "user2", 0 )
 1893      ROM_LOAD( "beedisk.img", 0x000000, 0x1c2000, NO_DUMP )
 1894  ROM_END
 1895  
 1896  ROM_START( quizvadr )
 1897      ROM_REGION( 0x10000, "audiocpu", 0 )
 1898      ROM_LOAD( "q6809.bin", 0x08000, 0x8000, CRC(a74dff10) SHA1(87578694a022dc3d7ade9cc76d387c1ae5fc74d9) )
 1899  
 1900      ROM_REGION( 0x10000, "altrevs", 0 )
 1901      ROM_LOAD( "qvadrint", 0x08000, 0x08000, CRC(4c729943) SHA1(ab4e0fb6cfc66540ea1e9e36eebdf85f65c5fd2a) )
 1902  
 1903      ROM_REGION( 0x200000, "user1", 0 )
 1904      ROM_LOAD( "5947011r.0", 0x000000, 0x80000, CRC(cac43c97) SHA1(3af529cd0f8ec57dd3596f5bca7b9c74cff171e4) )
 1905      ROM_LOAD( "5947011r.1", 0x080000, 0x80000, CRC(120018dc) SHA1(cd153d2b7ed535b04dbcaf189d2fc96fe3c5b466) )
 1906      ROM_LOAD( "5947011r.2", 0x100000, 0x80000, CRC(689b3b5a) SHA1(ea32d18acfd380de822efff4f2c95ce9873a33a2) )
 1907      ROM_LOAD( "5947011r.3", 0x180000, 0x80000, CRC(c38dafeb) SHA1(d693387a5c3cde34c9d581f81a08a5fbc6f753f2) )
 1908  
 1909      ROM_REGION( 0x20000, "upd", 0 )
 1910      ROM_LOAD( "185snd2.bin", 0x00000, 0x10000, CRC(e36eccc2) SHA1(cfd8ca4c71528ea4e229074016240681b6de37cd) )
 1911      ROM_LOAD( "184snd1.bin", 0x10000, 0x10000, CRC(aac058e8) SHA1(39e59ad9524130fc3bd8d46e1aa78bc4daf04e39) )
 1912  ROM_END
 1913  
 1914  ROM_START( qos )
 1915      ROM_REGION( 0x10000, "audiocpu", 0 )
 1916      ROM_LOAD( "39360107.bin", 0x08000, 0x8000, CRC(20844655) SHA1(b67c7f7bbabf6d5139b8ad8cbb5f8cc3f28e9cc7) )
 1917  
 1918      ROM_REGION( 0x200000, "user1", 0 )
 1919      ROM_LOAD( "95000338.rm0", 0x000000, 0x80000, CRC(96918aae) SHA1(849ce7b8eccc89c45aacc840a73935f95788a141) )
 1920      ROM_LOAD( "95000339.rm1", 0x080000, 0x80000, CRC(b4c6dcc0) SHA1(56d8761766dfbd5b0e71f8c3ca575e88f1bc9929) )
 1921      ROM_LOAD( "95000340.rm2", 0x100000, 0x80000, CRC(66d121fd) SHA1(ac65cc0ac6b0a41e78a3159c21ee44f765bdb5c8) )
 1922      ROM_LOAD( "95000341.rm3", 0x180000, 0x80000, CRC(ef13658d) SHA1(240bc589900214eac79c91a531f254a9ac2f4ef6) )
 1923  
 1924      ROM_REGION( 0x20000, "upd", 0 )
 1925      ROM_LOAD( "snd1_218.ic7", 0x00000, 0x10000, CRC(061f496d) SHA1(653d16454d909c034191813b37d14010da7258c6) )
 1926      ROM_LOAD( "snd2_219.ic8", 0x10000, 0x10000, CRC(d7874a47) SHA1(5bbd4040c7c0299e8cc135e6c6cd05370b260e9b) )
 1927  ROM_END
 1928  
 1929  ROM_START( qosa )
 1930      ROM_REGION( 0x10000, "audiocpu", 0 )
 1931      ROM_LOAD( "qos_nondata_68f4.bin", 0x08000, 0x8000, CRC(5f40005a) SHA1(180017acf6b432bc135d1090099fdf99f1e3583a) )
 1932  
 1933      ROM_REGION( 0x200000, "user1", 0 )
 1934      ROM_LOAD( "95000338.rm0", 0x000000, 0x80000, CRC(96918aae) SHA1(849ce7b8eccc89c45aacc840a73935f95788a141) )
 1935      ROM_LOAD( "95000339.rm1", 0x080000, 0x80000, CRC(b4c6dcc0) SHA1(56d8761766dfbd5b0e71f8c3ca575e88f1bc9929) )
 1936      ROM_LOAD( "95000340.rm2", 0x100000, 0x80000, CRC(66d121fd) SHA1(ac65cc0ac6b0a41e78a3159c21ee44f765bdb5c8) )
 1937      ROM_LOAD( "95000341.rm3", 0x180000, 0x80000, CRC(ef13658d) SHA1(240bc589900214eac79c91a531f254a9ac2f4ef6) )
 1938  
 1939      ROM_REGION( 0x20000, "upd", 0 )
 1940      ROM_LOAD( "snd1_218.ic7", 0x00000, 0x10000, CRC(061f496d) SHA1(653d16454d909c034191813b37d14010da7258c6) )
 1941      ROM_LOAD( "snd2_219.ic8", 0x10000, 0x10000, CRC(d7874a47) SHA1(5bbd4040c7c0299e8cc135e6c6cd05370b260e9b) )
 1942  ROM_END
 1943  
 1944  ROM_START( qosb )
 1945      ROM_REGION( 0x10000, "audiocpu", 0 )
 1946      ROM_LOAD( "95740599.bin", 0x08000, 0x8000, CRC(bf1e321f) SHA1(51f18620f22ba2a1b110954284ddf00614d51a0e) )
 1947  
 1948      ROM_REGION( 0x200000, "user1", 0 )
 1949      ROM_LOAD( "rom0_306.bin", 0x000000, 0x80000, CRC(c26c8f83) SHA1(6949027e1fe241cbb2e1cbbce18e47bcb0d84550) )
 1950      ROM_LOAD( "rom1_307.bin", 0x080000, 0x80000, CRC(94611c03) SHA1(81f545ff96ff3d44285315400da94d870c89f896) )
 1951      ROM_LOAD( "rom2_308.bin", 0x100000, 0x80000, CRC(f5572726) SHA1(e109265c5571d21213a6f405a13459e7bc6699bc) )
 1952      ROM_LOAD( "rom3_309.bin", 0x180000, 0x80000, CRC(1b5edfa8) SHA1(348488debd4aa52f064e351ed0c082274da1db2b) )
 1953  
 1954      ROM_REGION( 0x20000, "upd", 0 )
 1955      ROM_LOAD( "snd1_218.ic7", 0x00000, 0x10000, CRC(061f496d) SHA1(653d16454d909c034191813b37d14010da7258c6) )
 1956      ROM_LOAD( "snd2_219.ic8", 0x10000, 0x10000, CRC(d7874a47) SHA1(5bbd4040c7c0299e8cc135e6c6cd05370b260e9b) )
 1957  
 1958      /* there is a set close to this with
 1959  
 1960          ROM_LOAD( "qosrom0", 0x0000, 0x080000, CRC(4f150634) SHA1(beb1d3c212b189f3baa08fe454e83f30108be08e) )
 1961          qosrom1 = rom1_307.bin          qosb       A Question of Sport (39-960-089)
 1962          ROM_LOAD( "qosrom2", 0x0000, 0x080000, CRC(c39737db) SHA1(ccfdb19dab3af064db44e6022248aef98749bc97) )
 1963          ROM_LOAD( "qosrom3", 0x0000, 0x080000, CRC(785b8ff9) SHA1(61b31e0e60c31ecb4b179bfe008a96155d939709) )
 1964          ROM_LOAD( "qossnd1", 0x0000, 0x010000, CRC(888a29f8) SHA1(0e5aa9db54e783708ece1e8c7bffb10d994ab384) )
 1965  
 1966         but it simply looks like a bad dump, rom3 is an alt 'rom 2' and the others are mostly the same as qosb
 1967      */
 1968  
 1969  ROM_END
 1970  
 1971  
 1972  GAME( 1989, inquiztr, 0         ,   bfcobra, bfcobra, bfcobra_state, bfcobra, ROT0, "BFM", "Inquizitor",                       GAME_NOT_WORKING )
 1973  GAME( 1990, escounts, 0         ,   bfcobra, bfcobra, bfcobra_state, bfcobra, ROT0, "BFM", "Every Second Counts (39-360-053)", GAME_IMPERFECT_GRAPHICS )
 1974  GAME( 1991, trebltop, 0         ,   bfcobra, bfcobra, bfcobra_state, bfcobra, ROT0, "BFM", "Treble Top (39-360-070)",          GAME_IMPERFECT_GRAPHICS )
 1975  GAME( 1991, beeline,  0         ,   bfcobra, bfcobra, bfcobra_state, bfcobra, ROT0, "BFM", "Beeline (39-360-075)",             GAME_NOT_WORKING | GAME_IMPERFECT_GRAPHICS )
 1976  GAME( 1991, quizvadr, 0         ,   bfcobra, bfcobra, bfcobra_state, bfcobra, ROT0, "BFM", "Quizvaders (39-360-078)",          GAME_IMPERFECT_GRAPHICS )
 1977  GAME( 1992, qos,      0         ,   bfcobra, bfcobra, bfcobra_state, bfcobra, ROT0, "BFM", "A Question of Sport (set 1, 39-960-107)", GAME_IMPERFECT_GRAPHICS )
 1978  GAME( 1992, qosa,     qos       ,   bfcobra, bfcobra, bfcobra_state, bfcobra, ROT0, "BFM", "A Question of Sport (set 2, 39-960-099)", GAME_IMPERFECT_GRAPHICS )
 1979  GAME( 1992, qosb,     qos       ,   bfcobra, bfcobra, bfcobra_state, bfcobra, ROT0, "BFM", "A Question of Sport (set 3, 39-960-089)", GAME_IMPERFECT_GRAPHICS )