Viewing File: <root>/src/mame/drivers/magicard.c

    1  /******************************************************************************
    2  
    3    MAGIC CARD - IMPERA
    4    -------------------
    5  
    6    Preliminary driver by Roberto Fresca, David Haywood & Angelo Salese
    7  
    8  
    9    Games running on this hardware:
   10  
   11    * Magic Card (set 1),        Impera, 199?.
   12    * Magic Card (set 2),        Impera, 199?.
   13    * Magic Card (set 3),        Impera, 199?.
   14    * Magic Card Export 94,      Impera, 1994.
   15    * Magic Card Jackpot (4.01), Impera, 1998.
   16    * Magic Lotto Export (5.03), Impera, 1998.
   17  
   18  
   19  *******************************************************************************
   20  
   21  
   22      *** Hardware Notes ***
   23  
   24      These are actually the specs of the Philips CD-i console.
   25  
   26      Identified:
   27  
   28      - CPU:  1x Philips SCC 68070 CCA84 (16 bits Microprocessor, PLCC) @ 15 MHz
   29      - VSC:  1x Philips SCC 66470 CAB (Video and System Controller, QFP)
   30  
   31      - Protection: 1x Dallas TimeKey DS1207-1 (for book-keeping protection)
   32  
   33      - Crystals:   1x 30.0000 MHz.
   34                    1x 19.6608 MHz.
   35  
   36      - PLDs:       1x PAL16L8ACN
   37                    1x PALCE18V8H-25
   38  
   39  
   40  *******************************************************************************
   41  
   42  
   43      *** General Notes ***
   44  
   45      Impera released "Magic Card" in a custom 16-bits PCB.
   46      The hardware was so expensive and they never have reached the expected sales,
   47      so... they ported the game to Impera/Funworld 8bits boards, losing part of
   48      graphics and sound/music quality. The new product was named "Magic Card II".
   49  
   50  
   51  *******************************************************************************
   52  
   53     Magic Card Jackpot 4.01
   54    (Also Magic Lotto Export)
   55    -------------------------
   56  
   57    PCB Layout:
   58     __________________________________________________________________________________________________
   59    |                                                                                                  |
   60    |                       SERIAL NUMBER                                                              |___
   61    |                                                                                                  (A)_|
   62    |  __     _____             ___________        _________                                            ___|
   63    | |  |   /     \           |9524 GNN   |      |YMZ284-D |                                           ___|
   64    | |  |  |BATTERY|          |HM514270AJ8|      |_________|                                           ___|
   65    | |A |  |  +3V  |          |___________|                                                            ___|
   66    | |  |  |       |                                       __________________         ________     __  ___|
   67    | |  |   \_____/            ___________                |                  |       |ULN2803A|   |..| ___|
   68    | |__|                     |9524 GNN   |               |  MUSIC           |       |________|   |..| ___|
   69    |                          |HM514270AJ8|               |  TR9C1710-11PCA  |                    |..|(J)_|
   70    |                          |___________|               |  SA119X/9612     |       _________    |..||
   71    |    ___    ___                                        |__________________|      |74HC273N |   |..||
   72    |   |   |  |   |                                                                 |_________|   |..||
   73    |   |   |  |   |                                                                               |..||
   74    |   | B |  | B |                                     _________                    _________    |..||
   75    |   |   |  |   |                                    | 74HC04N |                  |74HC245N |   |__||
   76    |   |   |  |   |                                    |_________|                  |_________|       |___
   77    |   |___|  |___|                                                                                   A___|
   78    |                                                                                                   ___|
   79    |    _____                  ______________                                                          ___|
   80    |   |     |                |              |                                        ________         ___|
   81    |   |     |                |  PHILIPS     |     ___    ___________    ________    |ULN2803A|        ___|
   82    |   |     | EI79465--A/02  |  SCC66470CAB |    | D |  |PIC16F84-10|  |   E    |   |________|        ___|
   83    |   |  C  | LPL-CPU V4.0   |  172632=1/2  |    |___|  |___________|  |________|                     ___|
   84    |   |     | MULTI GAME     |  DfD0032I3   |                                       _________         ___|
   85    |   |     | 8603186        |              |                                      |74HC273N |        ___|
   86    |   |     |                |              |                                      |_________|        ___|
   87    |   |     |                |              |                                                         ___|
   88    |   |_____|                |______________|                                 _     _________         ___|
   89    |                                                                          |G|   |74HC245N |        ___|
   90    |                                                                          |_|   |_________|        ___|
   91    |   _______   _______                                                                               ___|
   92    |  |]     [| |IC21   |                                 ______             ___                       ___|
   93    |  |]  E  [| |       |                                |ALTERA|           |___|                __    ___|
   94    |  |]  M  [| |       |                                | MAX  |             F      _________  |..|   ___|
   95    |  |]  P  [| | MAGIC |     ________________           |      |                   |74HC245N | |..|   ___|
   96    |  |]  T  [| | CARD  |    |                |          |EPM712|                   |_________| |..|   ___|
   97    |  |]  Y  [| |JACKPOT|    |   PHILIPS      |          |8SQC10|                               |..|   ___|
   98    |  |]     [| |       |    |  SCC68070CCA84 |          |0-15  |                               |..|   ___|
   99    |  |]  S  [| |Version|    |  213140-1      |          |______|      X_TAL's                  |__|   ___|
  100    |  |]  O  [| |   4.01|    |  DfD0103V3     |                      _   _   _                         ___|
  101    |  |]  C  [| |       |    |                |    ALL RIGHTS       | | | | | |                        ___|
  102    |  |]  K  [| |Vnr.:  |    |                |    BY  IMPERA       |1| |2| |3|                        ___|
  103    |  |]  E  [| |11.7.98|    |                |                     |_| |_| |_|                        ___|
  104    |  |]  T  [| |       |    |                |                                                        ___|
  105    |  |]     [| |       |    |________________|                                                        ___|
  106    |  |]_____[| |27C4002|                                                                              ___|
  107    |  |_______| |_______|                               ___________                                    ___|
  108    |    ___________________                            |RTC2421 A  |                                   ___|
  109    |   |   :::::::::::::   |                           |___________|                                  Z___|
  110    |   |___________________|                                                                          |
  111    |__________________________________________________________________________________________________|
  112  
  113  
  114    Xtal 1: 30.000 MHz.
  115    Xtal 2:  8.000 MHz.
  116    Xtal 3: 19.660 MHz.
  117  
  118  
  119    A = LT 0030 / LTC695CN / U18708
  120    B = NEC Japan / D43256BGU-70LL / 0008XD041
  121    C = MX B9819 / 29F1610MC-12C3 / M25685 / TAIWAN
  122    D = 24C02C / 24C04 (Serial I2C Bus EEPROM with User-Defined Block Write Protection).
  123    E = P0030SG / CD40106BCN
  124    F = 74HCU04D
  125    G = 74HC74D
  126  
  127  
  128    Silkscreened on the solder side:
  129  
  130    LEOTS.
  131    2800
  132    AT&S-F0 ML 94V-0
  133  
  134    IMPERA AUSTRIA          -------
  135    TEL: 0043/7242/27116     V 4.0
  136    FAX: 0043/7242/27053    -------
  137  
  138  
  139  *******************************************************************************
  140  
  141    TODO:
  142  
  143    - Proper handling of the 68070 (68k with 32 address lines instead of 24)
  144      & handle the extra features properly (UART,DMA,Timers etc.)
  145  
  146    - Proper emulation of the 66470 Video Chip (still many unhandled features)
  147  
  148    - Inputs;
  149  
  150    - Unknown sound chip (it's an ADPCM with eight channels);
  151  
  152    - Many unknown memory maps;
  153  
  154    - Proper memory map and machine driver for magicardj & magicle.
  155      (different sound chip, extra undumped rom and PIC controller)
  156  
  157  
  158  *******************************************************************************/
  159  
  160  
  161  #define CLOCK_A XTAL_30MHz
  162  #define CLOCK_B XTAL_8MHz
  163  #define CLOCK_C XTAL_19_6608MHz
  164  
  165  #include "emu.h"
  166  #include "cpu/m68000/m68000.h"
  167  #include "sound/2413intf.h"
  168  
  169  
  170  class magicard_state : public driver_device
  171  {
  172  public:
  173      magicard_state(const machine_config &mconfig, device_type type, const char *tag)
  174          : driver_device(mconfig, type, tag) ,
  175          m_magicram(*this, "magicram"),
  176          m_pcab_vregs(*this, "pcab_vregs"),
  177          m_scc68070_ext_irqc_regs(*this, "scc_xirqc_regs"),
  178          m_scc68070_iic_regs(*this, "scc_iic_regs"),
  179          m_scc68070_uart_regs(*this, "scc_uart_regs"),
  180          m_scc68070_timer_regs(*this, "scc_timer_regs"),
  181          m_scc68070_int_irqc_regs(*this, "scc_iirqc_regs"),
  182          m_scc68070_dma_ch1_regs(*this, "scc_dma1_regs"),
  183          m_scc68070_dma_ch2_regs(*this, "scc_dma2_regs"),
  184          m_scc68070_mmu_regs(*this, "scc_mmu_regs"){ }
  185  
  186      required_shared_ptr<UINT16> m_magicram;
  187      required_shared_ptr<UINT16> m_pcab_vregs;
  188      required_shared_ptr<UINT16> m_scc68070_ext_irqc_regs;
  189      required_shared_ptr<UINT16> m_scc68070_iic_regs;
  190      required_shared_ptr<UINT16> m_scc68070_uart_regs;
  191      required_shared_ptr<UINT16> m_scc68070_timer_regs;
  192      required_shared_ptr<UINT16> m_scc68070_int_irqc_regs;
  193      required_shared_ptr<UINT16> m_scc68070_dma_ch1_regs;
  194      required_shared_ptr<UINT16> m_scc68070_dma_ch2_regs;
  195      required_shared_ptr<UINT16> m_scc68070_mmu_regs;
  196      struct { int r,g,b,offs,offs_internal; } m_pal;
  197      DECLARE_READ16_MEMBER(test_r);
  198      DECLARE_WRITE16_MEMBER(paletteram_io_w);
  199      DECLARE_READ16_MEMBER(philips_66470_r);
  200      DECLARE_WRITE16_MEMBER(philips_66470_w);
  201      DECLARE_READ16_MEMBER(scc68070_ext_irqc_r);
  202      DECLARE_WRITE16_MEMBER(scc68070_ext_irqc_w);
  203      DECLARE_READ16_MEMBER(scc68070_iic_r);
  204      DECLARE_WRITE16_MEMBER(scc68070_iic_w);
  205      DECLARE_READ16_MEMBER(scc68070_uart_r);
  206      DECLARE_WRITE16_MEMBER(scc68070_uart_w);
  207      DECLARE_READ16_MEMBER(scc68070_timer_r);
  208      DECLARE_WRITE16_MEMBER(scc68070_timer_w);
  209      DECLARE_READ16_MEMBER(scc68070_int_irqc_r);
  210      DECLARE_WRITE16_MEMBER(scc68070_int_irqc_w);
  211      DECLARE_READ16_MEMBER(scc68070_dma_ch1_r);
  212      DECLARE_WRITE16_MEMBER(scc68070_dma_ch1_w);
  213      DECLARE_READ16_MEMBER(scc68070_dma_ch2_r);
  214      DECLARE_WRITE16_MEMBER(scc68070_dma_ch2_w);
  215      DECLARE_READ16_MEMBER(scc68070_mmu_r);
  216      DECLARE_WRITE16_MEMBER(scc68070_mmu_w);
  217      DECLARE_DRIVER_INIT(magicard);
  218      virtual void machine_reset();
  219      virtual void video_start();
  220      UINT32 screen_update_magicard(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
  221      INTERRUPT_GEN_MEMBER(magicard_irq);
  222  };
  223  
  224  
  225  /*************************
  226  *     Video Hardware     *
  227  *************************/
  228  
  229  /*
  230  66470
  231  video and system controller
  232  19901219/wjvg
  233  */
  234  /*
  235  TODO: check this register,doesn't seem to be 100% correct.
  236  1fffe0  csr = control and status register
  237      w 00...... ........ DM = slow timing speed, normal dram mode
  238      w 01...... ........ DM = fast timing speed, page dram mode
  239      w 10...... ........ DM = fast timing speed, nibble dram mode
  240      w 11...... ........ DM = slow timing speed, dual-port vram mode
  241      w ..1..... ........ TD = 256/64 k dram's
  242      w ...1.... ........ CG = enable character generator
  243      w ....1... ........ DD = rom data acknowledge delay
  244      w .....1.. ........ ED = early dtack
  245      w ......0. ........ not used
  246      w .......1 ........ BE  = enable bus error (watchdog timer)
  247     r  ........ 1.......  DA  = vertical display active
  248     r  ........ .1......  FG  = set during frame grabbing (if fg in dcr set)
  249     r  ........ ..xxx...  not used
  250     r  ........ .....1..  IT2 = intn active
  251     r  ........ ......1.  IT1 = pixac free and intn active
  252     r  ........ .......1  BE  = bus error generated by watchdog timer
  253  */
  254  
  255  /*63 at post test,6d all the time.*/
  256  #define SCC_CSR_VREG    (state->m_pcab_vregs[0x00/2] & 0xffff)
  257  #define SCC_CG_VREG     ((SCC_CSR_VREG & 0x10)>>4)
  258  
  259  /*
  260  1fffe2  dcr = display command register
  261      w 1....... ........  DE = enable display
  262      w .00..... ........  CF = 20   MHz (or 19.6608 MHz)
  263      w .01..... ........  CF = 24   MHz
  264      w .10..... ........  CF = 28.5 MHz
  265      w .11..... ........  CF = 30   MHz
  266      w ...1.... ........  FD = 60/50 Hz frame duration
  267      w ....00.. ........  SM/SS = non-interlaced scan mode
  268      w ....01.. ........  SM/SS = double frequency scan mode
  269      w ....10.. ........  SM/SS = interlaced scan mode
  270      w ....11.. ........  SM/SS = interlaced field repeat scan mode
  271      w ......1. ........  LS = full screen/border
  272      w .......1 ........  CM = logical/physical screen
  273      w ........ 1.......  FG = 4/8 bits per pixel
  274      w ........ .1......  DF = enable frame grabbing
  275      w ........ ..00....  IC/DC = ICA and DCA inactive
  276      w ........ ..01....  IC/DC = ICA active, reduced DCA mode (DCA sz=16 byts)
  277      w ........ ..10....  IC/DC = ICA active, DCA inactive
  278      w ........ ..11....  IC/DC = ICA active, DCA active (DCA size=64 bytes)
  279      w ........ ....aaaa  VSR:H = video start address (MSB's)
  280  */
  281  
  282  #define SCC_DCR_VREG    (state->m_pcab_vregs[0x02/2] & 0xffff)
  283  #define SCC_DE_VREG     ((SCC_DCR_VREG & 0x8000)>>15)
  284  #define SCC_FG_VREG     ((SCC_DCR_VREG & 0x0080)>>7)
  285  #define SCC_VSR_VREG_H  ((SCC_DCR_VREG & 0xf)>>0)
  286  
  287  /*
  288  1fffe4  vsr = video start register
  289      w aaaaaaaa aaaaaaaa  VSR:L = video start address (LSB's)
  290  */
  291  
  292  #define SCC_VSR_VREG_L  (state->m_pcab_vregs[0x04/2] & 0xffff)
  293  #define SCC_VSR_VREG    ((SCC_VSR_VREG_H)<<16) | (SCC_VSR_VREG_L)
  294  
  295  /*
  296  1fffe6  bcr = border colour register
  297      w ........ nnnnnnnn  in 8 bit mode
  298      w ........ nnnn....  in 4 bit mode
  299  */
  300  /*
  301  (Note: not present on the original vreg listing)
  302  1fffe8 dcr2 = display command register 2
  303      w x....... ........  not used
  304      w .nn..... ........  OM = lower port of the video mode (with CM)
  305      w ...1.... ........  ID = Indipendent DCA bit
  306      w ....nn.. ........  MF = Mosaic Factor (2,4,8,16)
  307      w ......nn ........  FT = File Type (0/1 = bitmap, 2 = RLE, 3 = Mosaic)
  308      w ........ xxxx....  not used
  309      w ........ ....aaaa  "data" (dunno the purpose...)
  310  */
  311  #define SCC_DCR2_VREG  (state->m_pcab_vregs[0x08/2] & 0xffff)
  312  
  313  /*
  314  (Note: not present on the original vreg listing)
  315  1fffea dcp = ???
  316      w aaaaaaaa aaaaaa--  "data" (dunno the purpose...)
  317      w -------- ------xx not used
  318  */
  319  
  320  /*
  321  1fffec  swm = selective write mask register
  322      w nnnnnnnn ........  mask
  323  */
  324  /*
  325  1fffee  stm = selective mask register
  326      w ........ nnnnnnnn  mask
  327  */
  328  /*
  329  1ffff0  a = source register a
  330      w nnnnnnnn nnnnnnnn  source
  331  */
  332  #define SCC_SRCA_VREG  (state->m_pcab_vregs[0x10/2] & 0xffff)
  333  
  334  /*
  335  1ffff2  b = destination register b
  336     rw nnnnnnnn nnnnnnnn  destination
  337  */
  338  
  339  #define SCC_DSTB_VREG  (state->m_pcab_vregs[0x12/2] & 0xffff)
  340  
  341  /*
  342  1ffff4  pcr = pixac command register
  343      w 1....... ........  4N  = 8/4 bits per pixel
  344      w .1....00 ....x00.  COL = enable colour2 function
  345      w .1....00 .....01.  COL = enable colour1 function
  346      w .1...0.. .....10.  COL = enable bcolour2 function
  347      w .1...0.. .....11.  COL = enable bcolour1 function
  348      w ..1..000 ....x00.  EXC = enable exchange function
  349      w ..1..000 .....01.  EXC = enable swap function
  350      w ..1..000 .....10.  EXC = enable inverted exchange function
  351      w ..1..000 .....11.  EXC = enable inverted swap function
  352      w ...1..0. ....x00.  CPY = enable copy type b function
  353      w ...1...0 ....x10.  CPY = enable copy type a function
  354      w ...1..0. .....01.  CPY = enable patch type b function
  355      w ...1...0 .....11.  CPY = enable patch type a function
  356      w ....1000 .....00.  CMP = enable compare function
  357      w ....1000 .....10.  CMP = enable compact function
  358      w .....1.. ........  RTL = manipulate right to left
  359      w ......1. ........  SHK = shrink picture by factor 2
  360      w .......1 ........  ZOM = zoom picture by factor 2
  361      w ........ nnnn....  LGF = logical function
  362      w ........ 0000....  LGF = d=r
  363      w ........ 0001....  LGF = d=~r
  364      w ........ 0010....  LGF = d=0
  365      w ........ 0011....  LGF = d=1
  366      w ........ 0100....  LGF = d=~(d^r)
  367      w ........ 0101....  LGF = d=d^r
  368      w ........ 0110....  LGF = d=d&r
  369      w ........ 0111....  LGF = d=~d&r
  370      w ........ 1000....  LGF = d=~d&~r
  371      w ........ 1001....  LGF = d=d&~r
  372      w ........ 1010....  LGF = d=~d|r
  373      w ........ 1011....  LGF = d=d|r
  374      w ........ 1100....  LGF = d=d|~r
  375      w ........ 1101....  LGF = d=~d|~r
  376      w ........ 1110....  LGF = d=d
  377      w ........ 1111....  LGF = d=~d
  378      w ........ ....1...  INV = invert transparancy state of source bits
  379      w ........ .....1..  BIT = copy:     enable copy type a
  380      w ........ .....1..  BIT = colour:   enable bcolour/colour
  381      w ........ .....1..  BIT = compare:  compact/compare
  382      w ........ ......1.  TT  = perform transparancy test
  383      w ........ .......0
  384  */
  385  
  386  #define SCC_PCR_VREG  (state->m_pcab_vregs[0x14/2] & 0xffff)
  387  
  388  /*
  389  1ffff6  mask = mask register
  390      w ........ ....nnnn  mask nibbles/0
  391  */
  392  /*
  393  1ffff8  shift = shift register
  394      w ......nn ........  shift by .. during source alignment
  395  */
  396  /*
  397  1ffffa  index = index register
  398      w ........ ......nn  bcolour: use bit .. in the source word
  399      w ........ ......nn  compact: nibble .. will hold the result
  400  */
  401  /*
  402  1ffffc  fc/bc = foreground/background colour register
  403      w nnnnnnnn ........  FC = foreground colour
  404      w ........ nnnnnnnn  BC = background colour
  405  */
  406  /*
  407  1ffffe  tc = transparent colour register
  408      w nnnnnnnn ........  transparent colour
  409  */
  410  
  411  
  412  void magicard_state::video_start()
  413  {
  414  }
  415  
  416  UINT32 magicard_state::screen_update_magicard(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
  417  {
  418      magicard_state *state = machine().driver_data<magicard_state>();
  419      int x,y;
  420      UINT32 count;
  421  
  422      bitmap.fill(get_black_pen(machine()), cliprect); //TODO
  423  
  424      if(!(SCC_DE_VREG)) //display enable
  425          return 0;
  426  
  427      count = ((SCC_VSR_VREG)/2);
  428  
  429      if(SCC_FG_VREG) //4bpp gfx
  430      {
  431          for(y=0;y<300;y++)
  432          {
  433              for(x=0;x<84;x++)
  434              {
  435                  UINT32 color;
  436  
  437                  color = ((m_magicram[count]) & 0x000f)>>0;
  438  
  439                  if(cliprect.contains((x*4)+3, y))
  440                      bitmap.pix32(y, (x*4)+3) = machine().pens[color];
  441  
  442                  color = ((m_magicram[count]) & 0x00f0)>>4;
  443  
  444                  if(cliprect.contains((x*4)+2, y))
  445                      bitmap.pix32(y, (x*4)+2) = machine().pens[color];
  446  
  447                  color = ((m_magicram[count]) & 0x0f00)>>8;
  448  
  449                  if(cliprect.contains((x*4)+1, y))
  450                      bitmap.pix32(y, (x*4)+1) = machine().pens[color];
  451  
  452                  color = ((m_magicram[count]) & 0xf000)>>12;
  453  
  454                  if(cliprect.contains((x*4)+0, y))
  455                      bitmap.pix32(y, (x*4)+0) = machine().pens[color];
  456  
  457                  count++;
  458              }
  459          }
  460      }
  461      else //8bpp gfx
  462      {
  463          for(y=0;y<300;y++)
  464          {
  465              for(x=0;x<168;x++)
  466              {
  467                  UINT32 color;
  468  
  469                  color = ((m_magicram[count]) & 0x00ff)>>0;
  470  
  471                  if(cliprect.contains((x*2)+1, y))
  472                      bitmap.pix32(y, (x*2)+1) = machine().pens[color];
  473  
  474                  color = ((m_magicram[count]) & 0xff00)>>8;
  475  
  476                  if(cliprect.contains((x*2)+0, y))
  477                      bitmap.pix32(y, (x*2)+0) = machine().pens[color];
  478  
  479                  count++;
  480              }
  481          }
  482      }
  483  
  484      return 0;
  485  }
  486  
  487  
  488  /*************************
  489  *      R/W Handlers      *
  490  *************************/
  491  
  492  READ16_MEMBER(magicard_state::test_r)
  493  {
  494      return machine().rand();
  495  }
  496  
  497  WRITE16_MEMBER(magicard_state::paletteram_io_w)
  498  {
  499      switch(offset*2)
  500      {
  501          case 0:
  502              m_pal.offs = data;
  503              m_pal.offs_internal = 0;
  504              break;
  505          case 4:
  506              break;
  507          case 2:
  508              switch(m_pal.offs_internal)
  509              {
  510                  case 0:
  511                      m_pal.r = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
  512                      m_pal.offs_internal++;
  513                      break;
  514                  case 1:
  515                      m_pal.g = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
  516                      m_pal.offs_internal++;
  517                      break;
  518                  case 2:
  519                      m_pal.b = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
  520                      palette_set_color(machine(), m_pal.offs, MAKE_RGB(m_pal.r, m_pal.g, m_pal.b));
  521                      m_pal.offs_internal = 0;
  522                      m_pal.offs++;
  523                      break;
  524              }
  525  
  526              break;
  527      }
  528  }
  529  
  530  READ16_MEMBER(magicard_state::philips_66470_r)
  531  {
  532      switch(offset)
  533      {
  534  //      case 0/2:
  535  //          return machine().rand(); //TODO
  536      }
  537  
  538      //printf("[%04x]\n",offset*2);
  539  
  540  
  541      return m_pcab_vregs[offset];
  542  }
  543  
  544  WRITE16_MEMBER(magicard_state::philips_66470_w)
  545  {
  546      COMBINE_DATA(&m_pcab_vregs[offset]);
  547  
  548  //  if(offset == 0x10/2)
  549  //  {
  550          //printf("%04x %04x %04x\n",data,m_pcab_vregs[0x12/2],m_pcab_vregs[0x14/2]);
  551          //m_pcab_vregs[0x12/2] = m_pcab_vregs[0x10/2];
  552  //  }
  553  }
  554  
  555  /* scc68070 specific stuff (to be moved) */
  556  
  557  READ16_MEMBER(magicard_state::scc68070_ext_irqc_r)
  558  {
  559      return m_scc68070_ext_irqc_regs[offset];
  560  }
  561  
  562  WRITE16_MEMBER(magicard_state::scc68070_ext_irqc_w)
  563  {
  564      m_scc68070_ext_irqc_regs[offset] = data;
  565  }
  566  
  567  READ16_MEMBER(magicard_state::scc68070_iic_r)
  568  {
  569      //printf("%04x\n",offset*2);
  570  
  571      switch(offset)
  572      {
  573          case 0x04/2: return m_scc68070_iic_regs[offset] & 0xef; //iic status register, bit 4 = pending irq
  574      }
  575  
  576      return m_scc68070_iic_regs[offset];
  577  }
  578  
  579  WRITE16_MEMBER(magicard_state::scc68070_iic_w)
  580  {
  581      m_scc68070_iic_regs[offset] = data;
  582  }
  583  
  584  READ16_MEMBER(magicard_state::scc68070_uart_r)
  585  {
  586      //printf("%02x\n",offset*2);
  587  
  588      switch(offset)
  589      {
  590          case 0x02/2: return machine().rand(); //uart mode register
  591      }
  592  
  593      return m_scc68070_uart_regs[offset];
  594  }
  595  
  596  WRITE16_MEMBER(magicard_state::scc68070_uart_w)
  597  {
  598      m_scc68070_uart_regs[offset] = data;
  599  }
  600  
  601  READ16_MEMBER(magicard_state::scc68070_timer_r)
  602  {
  603      return m_scc68070_timer_regs[offset];
  604  }
  605  
  606  WRITE16_MEMBER(magicard_state::scc68070_timer_w)
  607  {
  608      m_scc68070_timer_regs[offset] = data;
  609  }
  610  
  611  READ16_MEMBER(magicard_state::scc68070_int_irqc_r)
  612  {
  613      return m_scc68070_int_irqc_regs[offset];
  614  }
  615  
  616  WRITE16_MEMBER(magicard_state::scc68070_int_irqc_w)
  617  {
  618      m_scc68070_int_irqc_regs[offset] = data;
  619  }
  620  
  621  READ16_MEMBER(magicard_state::scc68070_dma_ch1_r)
  622  {
  623      return m_scc68070_dma_ch1_regs[offset];
  624  }
  625  
  626  WRITE16_MEMBER(magicard_state::scc68070_dma_ch1_w)
  627  {
  628      m_scc68070_dma_ch1_regs[offset] = data;
  629  }
  630  
  631  READ16_MEMBER(magicard_state::scc68070_dma_ch2_r)
  632  {
  633      return m_scc68070_dma_ch2_regs[offset];
  634  }
  635  
  636  WRITE16_MEMBER(magicard_state::scc68070_dma_ch2_w)
  637  {
  638      m_scc68070_dma_ch2_regs[offset] = data;
  639  }
  640  
  641  READ16_MEMBER(magicard_state::scc68070_mmu_r)
  642  {
  643      return m_scc68070_mmu_regs[offset];
  644  }
  645  
  646  WRITE16_MEMBER(magicard_state::scc68070_mmu_w)
  647  {
  648      m_scc68070_mmu_regs[offset] = data;
  649  
  650      switch(offset)
  651      {
  652          case 0x0000/2:
  653              if(data & 0x80) //throw an error if the (unemulated) MMU is enabled
  654                  fatalerror("SCC68070: MMU enable bit active\n");
  655              break;
  656      }
  657  }
  658  
  659  
  660  /*************************
  661  *      Memory Maps       *
  662  *************************/
  663  
  664  static ADDRESS_MAP_START( magicard_mem, AS_PROGRAM, 16, magicard_state )
  665  //  ADDRESS_MAP_GLOBAL_MASK(0x1fffff)
  666      AM_RANGE(0x00000000, 0x0017ffff) AM_MIRROR(0x7fe00000) AM_RAM AM_SHARE("magicram") /*only 0-7ffff accessed in Magic Card*/
  667      AM_RANGE(0x00180000, 0x001ffbff) AM_MIRROR(0x7fe00000) AM_RAM AM_REGION("maincpu", 0)
  668      /* 001ffc00-001ffdff System I/O */
  669      AM_RANGE(0x001ffc00, 0x001ffc01) AM_MIRROR(0x7fe00000) AM_READ(test_r)
  670      AM_RANGE(0x001ffc40, 0x001ffc41) AM_MIRROR(0x7fe00000) AM_READ(test_r)
  671      AM_RANGE(0x001ffd00, 0x001ffd05) AM_MIRROR(0x7fe00000) AM_WRITE(paletteram_io_w) //RAMDAC
  672      /*not the right sound chip,unknown type,it should be an ADPCM with 8 channels.*/
  673      AM_RANGE(0x001ffd40, 0x001ffd43) AM_MIRROR(0x7fe00000) AM_DEVWRITE8_LEGACY("ymsnd", ym2413_w, 0x00ff)
  674      AM_RANGE(0x001ffd80, 0x001ffd81) AM_MIRROR(0x7fe00000) AM_READ(test_r)
  675      AM_RANGE(0x001ffd80, 0x001ffd81) AM_MIRROR(0x7fe00000) AM_WRITENOP //?
  676      AM_RANGE(0x001fff80, 0x001fffbf) AM_MIRROR(0x7fe00000) AM_RAM //DRAM I/O, not accessed by this game, CD buffer?
  677      AM_RANGE(0x001fffe0, 0x001fffff) AM_MIRROR(0x7fe00000) AM_READWRITE(philips_66470_r,philips_66470_w) AM_SHARE("pcab_vregs") //video registers
  678      AM_RANGE(0x80001000, 0x8000100f) AM_READWRITE(scc68070_ext_irqc_r,scc68070_ext_irqc_w) AM_SHARE("scc_xirqc_regs") //lir
  679      AM_RANGE(0x80002000, 0x8000200f) AM_READWRITE(scc68070_iic_r,scc68070_iic_w) AM_SHARE("scc_iic_regs") //i2c
  680      AM_RANGE(0x80002010, 0x8000201f) AM_READWRITE(scc68070_uart_r,scc68070_uart_w) AM_SHARE("scc_uart_regs")
  681      AM_RANGE(0x80002020, 0x8000202f) AM_READWRITE(scc68070_timer_r,scc68070_timer_w) AM_SHARE("scc_timer_regs")
  682      AM_RANGE(0x80002040, 0x8000204f) AM_READWRITE(scc68070_int_irqc_r,scc68070_int_irqc_w) AM_SHARE("scc_iirqc_regs")
  683      AM_RANGE(0x80004000, 0x8000403f) AM_READWRITE(scc68070_dma_ch1_r,scc68070_dma_ch1_w) AM_SHARE("scc_dma1_regs")
  684      AM_RANGE(0x80004040, 0x8000407f) AM_READWRITE(scc68070_dma_ch2_r,scc68070_dma_ch2_w) AM_SHARE("scc_dma2_regs")
  685      AM_RANGE(0x80008000, 0x8000807f) AM_READWRITE(scc68070_mmu_r,scc68070_mmu_w) AM_SHARE("scc_mmu_regs")
  686  ADDRESS_MAP_END
  687  
  688  
  689  /*************************
  690  *      Input ports       *
  691  *************************/
  692  
  693  static INPUT_PORTS_START( magicard )
  694  INPUT_PORTS_END
  695  
  696  
  697  void magicard_state::machine_reset()
  698  {
  699      UINT16 *src    = (UINT16*)memregion("maincpu" )->base();
  700      UINT16 *dst    = m_magicram;
  701      memcpy (dst, src, 0x80000);
  702      machine().device("maincpu")->reset();
  703  }
  704  
  705  
  706  /*************************
  707  *    Machine Drivers     *
  708  *************************/
  709  
  710  /*Probably there's a mask somewhere if it REALLY uses irqs at all...irq vectors dynamically changes after some time.*/
  711  INTERRUPT_GEN_MEMBER(magicard_state::magicard_irq)
  712  {
  713      if(machine().input().code_pressed(KEYCODE_Z)) //vblank?
  714          device.execute().set_input_line_and_vector(1, HOLD_LINE,0xe4/4);
  715      if(machine().input().code_pressed(KEYCODE_X)) //uart irq
  716          device.execute().set_input_line_and_vector(1, HOLD_LINE,0xf0/4);
  717  }
  718  
  719  static MACHINE_CONFIG_START( magicard, magicard_state )
  720      MCFG_CPU_ADD("maincpu", SCC68070, CLOCK_A/2)    /* SCC-68070 CCA84 datasheet */
  721      MCFG_CPU_PROGRAM_MAP(magicard_mem)
  722      MCFG_CPU_VBLANK_INT_DRIVER("screen", magicard_state,  magicard_irq) /* no interrupts? (it erases the vectors..) */
  723  
  724      MCFG_SCREEN_ADD("screen", RASTER)
  725      MCFG_SCREEN_REFRESH_RATE(60)
  726      MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
  727      MCFG_SCREEN_SIZE(400, 300)
  728      MCFG_SCREEN_VISIBLE_AREA(0, 320-1, 0, 256-1) //dynamic resolution,TODO
  729      MCFG_SCREEN_UPDATE_DRIVER(magicard_state, screen_update_magicard)
  730  
  731      MCFG_PALETTE_LENGTH(0x100)
  732  
  733  
  734  
  735      MCFG_SPEAKER_STANDARD_MONO("mono")
  736      MCFG_SOUND_ADD("ymsnd", YM2413, CLOCK_A/12)
  737      MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
  738  MACHINE_CONFIG_END
  739  
  740  
  741  /*************************
  742  *        Rom Load        *
  743  *************************/
  744  
  745  ROM_START( magicard )
  746      ROM_REGION( 0x80000, "maincpu", 0 ) /* 68070 Code & GFX */
  747      ROM_LOAD16_WORD_SWAP( "magicorg.bin", 0x000000, 0x80000, CRC(810edf9f) SHA1(0f1638a789a4be7413aa019b4e198353ba9c12d9) )
  748  
  749      ROM_REGION( 0x0100, "sereeprom", 0 ) /* Serial EPROM */
  750      ROM_LOAD16_WORD_SWAP("mgorigee.bin",    0x0000, 0x0100, CRC(73522889) SHA1(3e10d6c1585c3a63cff717a0b950528d5373c781) )
  751  ROM_END
  752  
  753  ROM_START( magicarda )
  754      ROM_REGION( 0x80000, "maincpu", 0 ) /* 68070 Code & GFX */
  755      ROM_LOAD16_WORD_SWAP( "mcorigg2.bin", 0x00000, 0x20000, CRC(48546aa9) SHA1(23099a5e4c9f2c3386496f6d7f5bb7d435a6fb16) )
  756      ROM_RELOAD(                           0x40000, 0x20000 )
  757      ROM_LOAD16_WORD_SWAP( "mcorigg1.bin", 0x20000, 0x20000, CRC(c9e4a38d) SHA1(812e5826b27c7ad98142a0f52fbdb6b61a2e31d7) )
  758      ROM_RELOAD(                           0x40001, 0x20000 )
  759  
  760      ROM_REGION( 0x0100, "sereeprom", 0 ) /* Serial EPROM */
  761      ROM_LOAD("mgorigee.bin",    0x0000, 0x0100, CRC(73522889) SHA1(3e10d6c1585c3a63cff717a0b950528d5373c781) )
  762  ROM_END
  763  
  764  ROM_START( magicardb )
  765      ROM_REGION( 0x80000, "maincpu", 0 ) /* 68070 Code & GFX */
  766      ROM_LOAD16_WORD_SWAP( "mg_8.bin", 0x00000, 0x80000, CRC(f5499765) SHA1(63bcf40b91b43b218c1f9ec1d126a856f35d0844) )
  767  
  768      /*bigger than the other sets?*/
  769      ROM_REGION( 0x20000, "other", 0 ) /* unknown */
  770      ROM_LOAD16_WORD_SWAP("mg_u3.bin",   0x00000,    0x20000, CRC(2116de31) SHA1(fb9c21ca936532e7c342db4bcaaac31c478b1a35) )
  771  ROM_END
  772  
  773  ROM_START( magicardj )
  774      ROM_REGION( 0x80000, "maincpu", 0 ) /* 68070 Code & GFX */
  775      ROM_LOAD16_WORD_SWAP( "27c4002(__magicardj).ic21", 0x00000, 0x80000, CRC(ab2ed583) SHA1(a2d7148b785a8dfce8cff3b15ada293d65561c98) )
  776  
  777      ROM_REGION( 0x0100, "pic16f84", 0 ) /* protected */
  778      ROM_LOAD("pic16f84.ic29",   0x0000, 0x0100, BAD_DUMP CRC(0d968558) SHA1(b376885ac8452b6cbf9ced81b1080bfd570d9b91) )
  779  
  780      ROM_REGION( 0x200000, "other", 0 ) /* unknown contents */
  781      ROM_LOAD("29f1610mc.ic30",  0x000000, 0x200000, NO_DUMP )
  782  
  783      ROM_REGION( 0x0100, "sereeprom", 0 ) /* Serial EPROM */
  784      ROM_LOAD("24c02c.ic26", 0x0000, 0x0100, CRC(b5c86862) SHA1(0debc0f7e7c506e5a4e2cae152548d80ad72fc2e) )
  785  ROM_END
  786  
  787  /*
  788      Magic Card Export 94
  789    International Ver. 2.11a
  790  Vnr.29.07.94    CHECKSUM: A63D
  791  
  792  
  793  
  794  1 x Philips SCC66470CAB 383610
  795  1 x Philips SCC68070 CCA84 347141
  796  1 x ESI1 I9631
  797  1 x MUSIC TR9C1710-11PCA SA121X/9617
  798  1 x YAMAHA YM2149F 9614
  799  
  800  XTAL:
  801  
  802  Q1: 19.6608 Mhz
  803  Q2: 30.000 Mhz
  804  Q3: 3686.400  1Q08/95
  805  */
  806  
  807  ROM_START( magicarde )
  808      ROM_REGION( 0x80000, "maincpu", 0 ) /* 68070 Code & GFX */
  809      ROM_LOAD16_WORD_SWAP( "27c4002.ic21", 0x00000, 0x80000, CRC(b5f24412) SHA1(73ff05c19132932a419fef0d5dc985440ce70e83) )
  810  
  811      ROM_REGION( 0x0200, "pic16c54", 0 ) /* protected */
  812      ROM_LOAD("pic16c54.ic29",   0x0000, 0x0200, BAD_DUMP CRC(73224200) SHA1(c9a1038146647430759d570bb5626047a476a05b) )
  813  
  814      ROM_REGION( 0x0100, "sereeprom", 0 ) /* Serial EPROM */
  815      ROM_LOAD("st24c02.ic26",    0x0000, 0x0100, CRC(98287c67) SHA1(ad34e55c1ce4f77c27049dac88050ed3c94af1a0) )
  816  ROM_END
  817  
  818  ROM_START( magicle )
  819      ROM_REGION( 0x80000, "maincpu", 0 ) /* 68070 Code & GFX */
  820      ROM_LOAD16_WORD_SWAP( "27c4002.ic21", 0x00000, 0x80000, CRC(73328346) SHA1(fca5f8a93f25377e659c2b291674d706ca37400e) )
  821  
  822      ROM_REGION( 0x0100, "pic16f84", 0 ) /* protected */
  823      ROM_LOAD("pic16f84.ic29",   0x0000, 0x0100, BAD_DUMP CRC(0d968558) SHA1(b376885ac8452b6cbf9ced81b1080bfd570d9b91) )
  824  
  825      ROM_REGION( 0x200000, "other", 0 ) /* unknown contents */
  826      ROM_LOAD("29f1610mc.ic30",  0x000000, 0x200000, NO_DUMP )
  827  
  828      ROM_REGION( 0x0200, "sereeprom", 0 ) /* Serial EPROM */
  829      ROM_LOAD("24c04a.ic26", 0x0000, 0x0200, CRC(48c4f473) SHA1(5355313cc96f655096e13bfae78be3ba2dfe8a2d) )
  830  ROM_END
  831  
  832  
  833  /*************************
  834  *      Driver Init       *
  835  *************************/
  836  
  837  DRIVER_INIT_MEMBER(magicard_state,magicard)
  838  {
  839      //...
  840  }
  841  
  842  
  843  /*************************
  844  *      Game Drivers      *
  845  *************************/
  846  
  847  /*    YEAR  NAME       PARENT    MACHINE   INPUT     INIT      ROT    COMPANY   FULLNAME                    FLAGS... */
  848  
  849  GAME( 199?, magicard,  0,        magicard, magicard, magicard_state, magicard, ROT0, "Impera", "Magic Card (set 1)",        GAME_NO_SOUND | GAME_NOT_WORKING )
  850  GAME( 199?, magicarda, magicard, magicard, magicard, magicard_state, magicard, ROT0, "Impera", "Magic Card (set 2)",        GAME_NO_SOUND | GAME_NOT_WORKING )
  851  GAME( 199?, magicardb, magicard, magicard, magicard, magicard_state, magicard, ROT0, "Impera", "Magic Card (set 3)",        GAME_NO_SOUND | GAME_NOT_WORKING )
  852  GAME( 1994, magicarde, magicard, magicard, magicard, magicard_state, magicard, ROT0, "Impera", "Magic Card Export 94",      GAME_NO_SOUND | GAME_NOT_WORKING )
  853  GAME( 1998, magicardj, magicard, magicard, magicard, magicard_state, magicard, ROT0, "Impera", "Magic Card Jackpot (4.01)", GAME_NO_SOUND | GAME_NOT_WORKING )
  854  GAME( 2001, magicle,   0,        magicard, magicard, magicard_state, magicard, ROT0, "Impera", "Magic Lotto Export (5.03)", GAME_NO_SOUND | GAME_NOT_WORKING )