Viewing File: <root>/src/mame/drivers/magictg.c

    1  /***************************************************************************
    2  
    3      Magic the Gathering: Armageddon
    4  
    5      preliminary driver by Phil Bennett
    6  
    7  
    8  PCB Information (needs tidying:)
    9  
   10  
   11  TOP Board
   12  .20u    27c4001 stickered   U20
   13                  #1537 V1.0  a 1 was hadwritten over the 0
   14  
   15  .u7     stamped     (c) 1997
   16                  ACCLAIM COINOP
   17                  ARMAGEDDON
   18                  SND3 P/N 1605
   19                  9806 D
   20  
   21  
   22  .u8     stamped     (c) 1997 11/25/97
   23                  ACCLAIM COINOP
   24                  ARMAGEDDON
   25                  1534 SND0
   26                  9752 D
   27  
   28  .u13        stamped     (c) 1997 11/25/97
   29                  ACCLAIM COINOP
   30                  ARMAGEDDON
   31                  1536 SND2
   32                  9752 D
   33  
   34  .u14        stamped     (c) 1997 11/25/97
   35                  ACCLAIM COINOP
   36                  ARMAGEDDON
   37                  1535 SND1
   38                  9752 D
   39  
   40  Analog devices  ADSP 2181
   41  Xilinx      XC5202
   42  dt71256 x2
   43  Analog Devices  AD1866R
   44  
   45  Bottom board
   46  .u32    27c801      stickered   4
   47  .u33    27c801      stickered   3
   48  .u34    27c801      stickered   2
   49  .u35    27c801      stickered   1
   50  .u58    AT17C128    stickered   CC3E
   51  .u66    GAL16V8D
   52  
   53  Xilinx  XC4005E
   54  Xilinx  XC95108 stickered   ACCLAIM COIN-OP
   55                  CSC2_10.JED
   56                  B710/0B84
   57                  U40 p/N 1611
   58  
   59  3dFX    500-0003-03     x2
   60      BF1684.1
   61  TI  TVP3409
   62      V53C16258HK40       x24
   63      V53C511816500K60    x4
   64  2 big chips with heat sinks on them, one by each 3dFX part
   65  2 big chips with heat sinks on them, by the EPROMS
   66  14.31818 Oscillator by the TI part
   67  50.0000 Oscillator by EPROMS
   68  33.0000 Oscillator by the V53C511816500K60
   69  KM622560LG-7 by Battery
   70  
   71  Bottom daughter board
   72  All read as 29F800B
   73  .u9     stamped     (c) 1997
   74                  ACCLAIM COINOP
   75                  ARMAGEDDON S0
   76                  1514 11/25/97
   77                  9803 D
   78  
   79  
   80  .u10        stamped     (c) 1997
   81                  ACCLAIM COINOP
   82                  ARMAGEDDON S1
   83                  1515 11/25/97
   84                  9803 D
   85  
   86  .u11        stamped     (c) 1997
   87                  ACCLAIM COINOP
   88                  ARMAGEDDON S3
   89                  1517 11/25/97
   90                  9803 D
   91  
   92  .u12        stamped     (c) 1997
   93                  ACCLAIM COINOP
   94                  ARMAGEDDON S2
   95                  1516 11/25/97
   96                  9803 D
   97  
   98  .u20        stamped     (c) 1997
   99                  ACCLAIM COINOP
  100                  ARMAGEDDON K0
  101                  1543 11/25/97
  102                  9752 D
  103  
  104  Xilinx  XC4010E
  105  Zoran   ZR36120PQC
  106  Zoran   ZR36016PQC
  107  Xilinx  XC3120A
  108      DT72811
  109      DT71256 x2
  110      DT72271
  111  29.500000 osciallator by ZR36120PQC
  112  Medium size chip with heat sink on it
  113  
  114  ***************************************************************************/
  115  
  116  #include "emu.h"
  117  #include "cpu/mips/mips3.h"
  118  #include "cpu/adsp2100/adsp2100.h"
  119  #include "sound/dmadac.h"
  120  #include "video/voodoo.h"
  121  #include "machine/pci.h"
  122  
  123  
  124  /* TODO: Two 3Dfx Voodoo chipsets are used in SLI configuration */
  125  // #define USE_TWO_3DFX
  126  
  127  class magictg_state : public driver_device
  128  {
  129  public:
  130      magictg_state(const machine_config &mconfig, device_type type, const char *tag)
  131          : driver_device(mconfig, type, tag),
  132          m_mips(*this, "mips"),
  133          m_adsp(*this, "adsp"),
  134          m_pci(*this, "pcibus")
  135      ,
  136          m_adsp_pram(*this, "adsp_pram"){ }
  137  
  138      required_device<cpu_device>         m_mips;
  139      required_device<adsp2181_device>    m_adsp;
  140      required_device<pci_bus_legacy_device>      m_pci;
  141  
  142  
  143      /* ASIC */
  144      struct
  145      {
  146          UINT32 src_addr;
  147          UINT32 dst_addr;
  148          UINT32 ctrl;
  149          UINT32 count;
  150      } m_dma_ch[3];
  151  
  152  
  153      /* ADSP-2181 */
  154      required_shared_ptr<UINT32> m_adsp_pram;
  155  
  156      struct
  157      {
  158          UINT16 bdma_internal_addr;
  159          UINT16 bdma_external_addr;
  160          UINT16 bdma_control;
  161          UINT16 bdma_word_count;
  162      } m_adsp_regs;
  163  
  164  
  165      /* 3Dfx Voodoo */
  166      device_t*                           m_voodoo[2];
  167  
  168      struct
  169      {
  170          /* PCI */
  171          UINT32 command;
  172          UINT32 base_addr;
  173  
  174          UINT32 init_enable;
  175      } m_voodoo_pci_regs[2];
  176  
  177  
  178      struct
  179      {
  180          /* PCI */
  181          UINT32 command;
  182          UINT32 base_addr;
  183  
  184          /* Memory-mapped */
  185          UINT32 as_regs[19];
  186      } m_zr36120;
  187  
  188  
  189      DECLARE_READ32_MEMBER( zr36120_r );
  190      DECLARE_WRITE32_MEMBER( zr36120_w );
  191  
  192      DECLARE_READ32_MEMBER( f0_r );
  193      DECLARE_WRITE32_MEMBER( f0_w );
  194  
  195      DECLARE_READ32_MEMBER( unk_r );
  196      DECLARE_READ32_MEMBER( rand_r );
  197  
  198      DECLARE_READ32_MEMBER( serial_r );
  199      DECLARE_WRITE32_MEMBER( serial_w );
  200  
  201      DECLARE_READ32_MEMBER( adsp_idma_data_r );
  202      DECLARE_WRITE32_MEMBER( adsp_idma_data_w );
  203      DECLARE_WRITE32_MEMBER( adsp_idma_addr_w );
  204  
  205      DECLARE_READ32_MEMBER( adsp_status_r );
  206      DECLARE_READ16_MEMBER( adsp_control_r );
  207      DECLARE_WRITE16_MEMBER( adsp_control_w );
  208  
  209      void zr36120_reset();
  210  
  211  protected:
  212      virtual void machine_start();
  213      virtual void machine_reset();
  214      virtual void video_start();
  215  public:
  216      UINT32 screen_update_magictg(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
  217  };
  218  
  219  
  220  /*************************************
  221   *
  222   *  Machine initialization
  223   *
  224   *************************************/
  225  
  226  void magictg_state::machine_start()
  227  {
  228      m_voodoo[0] = machine().device("voodoo_0");
  229      m_voodoo[1] = machine().device("voodoo_1");
  230  }
  231  
  232  
  233  void magictg_state::machine_reset()
  234  {
  235      UINT8 *adsp_boot = (UINT8*)machine().root_device().memregion("adsp")->base();
  236  
  237      zr36120_reset();
  238  
  239      /* Load 32 program words (96 bytes) via BDMA */
  240      for (int i = 0; i < 32; i ++)
  241      {
  242          UINT32 word;
  243  
  244          word = adsp_boot[i*3 + 0] << 16;
  245          word |= adsp_boot[i*3 + 1] << 8;
  246          word |= adsp_boot[i*3 + 2];
  247  
  248          m_adsp_pram[i] = word;
  249      }
  250  }
  251  
  252  
  253  /*************************************
  254   *
  255   *  Video
  256   *
  257   *************************************/
  258  
  259  void magictg_state::video_start()
  260  {
  261  }
  262  
  263  UINT32 magictg_state::screen_update_magictg(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
  264  {
  265      return voodoo_update(m_voodoo[0], bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
  266  }
  267  
  268  
  269  /*************************************
  270   *
  271   *  3Dfx Voodoo
  272   *
  273   *************************************/
  274  
  275  static UINT32 pci_dev0_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask)
  276  {
  277      mame_printf_debug("PCI[0] READ: %x\n", reg);
  278      return 0x00000000; // TODO
  279  }
  280  
  281  static void pci_dev0_w(device_t *busdevice, device_t *device, int function, int reg, UINT32 data, UINT32 mem_mask)
  282  {
  283  }
  284  
  285  
  286  static UINT32 voodoo_0_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask)
  287  {
  288      magictg_state* state = device->machine().driver_data<magictg_state>();
  289      UINT32 val = 0;
  290  
  291      switch (reg)
  292      {
  293          case 0:
  294              val = 0x0001121a;
  295              break;
  296          case 0x10:
  297              val = state->m_voodoo_pci_regs[0].base_addr;
  298              break;
  299          case 0x40:
  300              val = state->m_voodoo_pci_regs[0].init_enable;
  301              break;
  302          default:
  303              mame_printf_debug("Voodoo[0] PCI R: %x\n", reg);
  304      }
  305      return val;
  306  }
  307  
  308  static void voodoo_0_pci_w(device_t *busdevice, device_t *device, int function, int reg, UINT32 data, UINT32 mem_mask)
  309  {
  310      magictg_state* state = device->machine().driver_data<magictg_state>();
  311  
  312      switch (reg)
  313      {
  314          case 0x04:
  315              state->m_voodoo_pci_regs[0].command = data & 0x3;
  316              break;
  317          case 0x10:
  318              if (data == 0xffffffff)
  319                  state->m_voodoo_pci_regs[0].base_addr = 0xff000000;
  320              else
  321                  state->m_voodoo_pci_regs[0].base_addr = data;
  322              break;
  323          case 0x40:
  324              state->m_voodoo_pci_regs[0].init_enable = data;
  325              voodoo_set_init_enable(state->m_voodoo[0], data);
  326              break;
  327  
  328          default:
  329              mame_printf_debug("Voodoo [%x]: %x\n", reg, data);
  330      }
  331  }
  332  
  333  #if defined(USE_TWO_3DFX)
  334  static UINT32 voodoo_1_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask)
  335  {
  336      magictg_state* state = space.machine().driver_data<magictg_state>();
  337      UINT32 val = 0;
  338  
  339      switch (reg)
  340      {
  341          case 0:
  342              val = 0x0001121a;
  343              break;
  344          case 0x10:
  345              val = state->m_voodoo_pci_regs[1].base_addr;
  346              break;
  347          case 0x40:
  348              val = state->m_voodoo_pci_regs[1].init_enable;
  349              break;
  350          default:
  351              mame_printf_debug("Voodoo[1] PCI R: %x\n", reg);
  352      }
  353      return val;
  354  }
  355  
  356  static void voodoo_1_pci_w(device_t *busdevice, device_t *device, int function, int reg, UINT32 data, UINT32 mem_mask)
  357  {
  358      magictg_state* state = space.machine().driver_data<magictg_state>();
  359  
  360      switch (reg)
  361      {
  362          case 0x04:
  363              voodoo_pci_regs[1].command = data & 0x3;
  364              break;
  365          case 0x10:
  366              if (data == 0xffffffff)
  367                  state->m_voodoo_pci_regs[1].base_addr = 0xff000000;
  368              else
  369                  state->m_voodoo_pci_regs[1].base_addr = data;
  370              break;
  371          case 0x40:
  372              state->m_voodoo_pci_regs[1].init_enable = data;
  373              voodoo_set_init_enable(state->m_voodoo[1], data);
  374              break;
  375  
  376          default:
  377              mame_printf_debug("Voodoo [%x]: %x\n", reg, data);
  378      }
  379  }
  380  #endif
  381  
  382  
  383  /*************************************
  384   *
  385   *  PinkEye (JPEG decoder)
  386   *
  387   *************************************/
  388  
  389  void magictg_state::zr36120_reset()
  390  {
  391      /* Reset PCI registers */
  392      m_zr36120.base_addr = 0;
  393  
  394      /* Reset application-specific registers */
  395      m_zr36120.as_regs[0x00/4] = (1 << 10) | 0x3ff;
  396      m_zr36120.as_regs[0x04/4] = (1 << 10) | 0x3ff;
  397      m_zr36120.as_regs[0x08/4] = (1 << 25) | (2 << 3) | 1;
  398      m_zr36120.as_regs[0x0c/4] = 0xfffffffc;
  399      m_zr36120.as_regs[0x10/4] = 0xfffffffc;
  400      m_zr36120.as_regs[0x14/4] = 0x00000000;
  401      m_zr36120.as_regs[0x18/4] = (7 << 25) | (0xf0 << 12) | 0x3ff;
  402      m_zr36120.as_regs[0x1c/4] = 0xfffffffc;
  403      m_zr36120.as_regs[0x20/4] = 0xfffffffc;
  404      m_zr36120.as_regs[0x24/4] = 0x000000ff;
  405      m_zr36120.as_regs[0x28/4] = 0x000000ff;
  406      m_zr36120.as_regs[0x2c/4] = 0xf0000000;
  407      m_zr36120.as_regs[0x30/4] = 0xfffffffc;
  408      m_zr36120.as_regs[0x34/4] = (1 << 29) | (1 << 28) | (3 << 12) | (1 << 8) | (6 << 1);
  409      m_zr36120.as_regs[0x38/4] = 0x00000000;
  410      m_zr36120.as_regs[0x3c/4] = 0x00000000;
  411      m_zr36120.as_regs[0x40/4] = 0x00000000;
  412      m_zr36120.as_regs[0x44/4] = 0x00000003;
  413      m_zr36120.as_regs[0x48/4] = 1 << 23;
  414  }
  415  
  416  static UINT32 zr36120_pci_r(device_t* busdevice, device_t* device, int function, int reg, UINT32 mem_mask)
  417  {
  418      magictg_state* state = busdevice->machine().driver_data<magictg_state>();
  419      UINT32 val = 0;
  420  
  421      switch (reg)
  422      {
  423          case 0x00:
  424              val = 0x612011de;
  425              break;
  426          case 0x04:
  427              val = state->m_zr36120.command;
  428              break;
  429          case 0x08:
  430              val = 0x04000002;
  431              break;
  432          case 0x10:
  433              val = state->m_zr36120.base_addr;
  434              break;
  435          default:
  436              mame_printf_debug("ZR36120 R[%x]\n", reg);
  437      }
  438      return val;
  439  }
  440  
  441  static void zr36120_pci_w(device_t* busdevice, device_t* device, int function, int reg, UINT32 data, UINT32 mem_mask)
  442  {
  443      magictg_state* state = busdevice->machine().driver_data<magictg_state>();
  444  
  445      switch (reg)
  446      {
  447          case 0x04:
  448              state->m_zr36120.command = data & 0x6;
  449              break;
  450          case 0x10:
  451              state->m_zr36120.base_addr = data & 0xfffff000;
  452              break;
  453          default:
  454              mame_printf_debug("ZR36120 [%x]: %x\n", reg, data);
  455      }
  456  }
  457  
  458  READ32_MEMBER( magictg_state::zr36120_r )
  459  {
  460      UINT32 res = 0;
  461  
  462      offset <<= 2;
  463  
  464      if (offset < 0x200)
  465      {
  466          switch (offset)
  467          {
  468              default:
  469                  res = m_zr36120.as_regs[offset];
  470          }
  471      }
  472      else
  473      {
  474          /* Post office */
  475          res = 0;//mame_rand(space.machine);//m_zr36120.as_regs[0x48/4];
  476      }
  477      mame_printf_debug("PINKEYE_R[%x]\n", offset);
  478      return res;
  479  }
  480  
  481  WRITE32_MEMBER( magictg_state::zr36120_w )
  482  {
  483      offset <<= 2;
  484  
  485      if (offset < 0x200)
  486      {
  487          mame_printf_debug("PINKEYE_W[%x] %x\n", offset, data);
  488          switch (offset)
  489          {
  490              case 0x00/4:
  491                  m_zr36120.as_regs[0] = data & 0x400fffff;
  492                  break;
  493              case 0x04/4:
  494                  m_zr36120.as_regs[1] = data & 0x400003ff;
  495                  break;
  496              default:
  497                  m_zr36120.as_regs[offset] = data;
  498          }
  499      }
  500      else
  501      {
  502          UINT32 guest = (data >> 20) & 3;
  503          UINT32 g_data = data & 0xff;
  504          UINT32 g_reg = (data >> 16) & 7;
  505  
  506          /* Direction - 0 for read, 1 for write */
  507          //  zr36120_guest_write(guest, g_data, g_reg);
  508          // 2 - ZR36050 JPEG decoder
  509          // 3 - ZR36016 color-space converter
  510          mame_printf_debug("GUEST (%.8x): %d  REG: %d  DATA: %x\n", data, guest, g_reg, g_data);
  511      }
  512  }
  513  
  514  
  515  /*************************************
  516   *
  517   *  System stuff
  518   *
  519   *************************************/
  520  
  521  READ32_MEMBER( magictg_state::unk_r )
  522  {
  523      /* Will not boot otherwise */
  524      return 0x6000;
  525  }
  526  
  527  READ32_MEMBER( magictg_state::rand_r )
  528  {
  529      return 0xffffffff;
  530  }
  531  
  532  WRITE32_MEMBER( magictg_state::serial_w )
  533  {
  534      if (offset == 0)
  535      {
  536          if (mem_mask == 0xff000000)
  537              printf("%c", data >> 24);
  538      }
  539  }
  540  
  541  WRITE32_MEMBER( magictg_state::f0_w )
  542  {
  543      int ch;
  544  
  545      offset *= 4;
  546  
  547      data = FLIPENDIAN_INT32(data);
  548      mem_mask = FLIPENDIAN_INT32(mem_mask);
  549  
  550      ch = ((offset >> 2) & 3) - 1;
  551  
  552      switch (offset)
  553      {
  554          case 0x804:
  555          case 0x808:
  556          case 0x80c:
  557              m_dma_ch[ch].count = data;
  558  //          mame_printf_debug("DMA%d COUNT: %.8x\n", ch, data);
  559              break;
  560  
  561          case 0x814:
  562          case 0x818:
  563          case 0x81c:
  564              m_dma_ch[ch].src_addr = data;
  565  //          mame_printf_debug("DMA%d SRC: %.8x\n", ch, data);
  566              break;
  567  
  568          case 0x824:
  569          case 0x828:
  570          case 0x82c:
  571              m_dma_ch[ch].dst_addr = data;
  572  //          mame_printf_debug("DMA%d DST: %.8x\n", ch, data);
  573              break;
  574  
  575          case 0x844:
  576          case 0x848:
  577          case 0x84c:
  578          {
  579              m_dma_ch[ch].ctrl = data;
  580  //          mame_printf_debug("DMA%d CTRL: %.8x\n", ch, data);
  581  
  582              if (data & 0x1000)
  583              {
  584                  UINT32 src_addr = m_dma_ch[ch].src_addr;
  585                  UINT32 dst_addr = m_dma_ch[ch].dst_addr;
  586                  //device_t *voodoo = dst_addr > 0xa000000 voodoo0 : voodoo1;
  587  
  588                  assert((src_addr & 3) == 0);
  589                  assert((dst_addr & 3) == 0);
  590  
  591                  while (m_dma_ch[ch].count > 3)
  592                  {
  593                      UINT32 src_dword = FLIPENDIAN_INT32(space.read_dword(src_addr));
  594                      space.write_dword(dst_addr, src_dword);
  595                      src_addr += 4;
  596                      dst_addr += 4;
  597                      m_dma_ch[ch].count -=4;
  598                  }
  599  
  600                  // FIXME!
  601                  if (m_dma_ch[ch].count & 3)
  602                  {
  603                      UINT32 src_dword = FLIPENDIAN_INT32(space.read_dword(src_addr));
  604                      UINT32 dst_dword = space.read_dword(dst_addr);
  605                      UINT32 mask = 0xffffffff >> ((m_dma_ch[ch].count & 3) << 3);
  606  
  607                      dst_dword = (dst_dword & ~mask) | (src_dword & mask);
  608                      space.write_dword(dst_addr, dst_dword);
  609                      m_dma_ch[ch].count = 0;
  610                  }
  611              }
  612  
  613              break;
  614          }
  615          case 0xcf8:
  616          {
  617              m_pci->write(space, 0, data, mem_mask);
  618              break;
  619          }
  620          case 0xcfc:
  621          {
  622              m_pci->write(space, 1, data, mem_mask);
  623              break;
  624          }
  625  //      default:
  626  //          mame_printf_debug("W: %.8x: %.8x\n", 0x0f000000 + offset, data);
  627      }
  628  }
  629  
  630  READ32_MEMBER( magictg_state::f0_r )
  631  {
  632      int ch;
  633      UINT32 val = 0;
  634      offset *= 4;
  635  
  636      ch = ((offset >> 2) & 3) - 1;
  637  
  638      switch (offset)
  639      {
  640          case 0x804:
  641          case 0x808:
  642          case 0x80c:
  643              val = m_dma_ch[ch].count;
  644              break;
  645  
  646          case 0x844:
  647          case 0x848:
  648          case 0x84c:
  649              val = 0x00000040; // Status of some sort
  650              break;
  651  
  652          case 0xcf8:
  653          {
  654              val = m_pci->read(space, 0, FLIPENDIAN_INT32(mem_mask));
  655              break;
  656          }
  657          case 0xcfc:
  658          {
  659              val = m_pci->read(space, 1, FLIPENDIAN_INT32(mem_mask));
  660              break;
  661          }
  662  //      default:
  663  //          mame_printf_debug("R: %.8x\n", 0x0f000000 + offset);
  664      }
  665  
  666      return FLIPENDIAN_INT32(val);
  667  }
  668  
  669  
  670  /*************************************
  671   *
  672   *  ADSP-2181 internals
  673   *
  674   *************************************/
  675  
  676  WRITE32_MEMBER( magictg_state::adsp_idma_data_w )
  677  {
  678      if (ACCESSING_BITS_16_31)
  679          m_adsp->idma_addr_w(data >> 16);
  680      else
  681          m_adsp->idma_addr_w(data & 0xffff);
  682  }
  683  
  684  READ32_MEMBER( magictg_state::adsp_idma_data_r )
  685  {
  686      // TODO: Set /IACK appropriately
  687      if (ACCESSING_BITS_0_15)
  688      {
  689          //mame_printf_debug("RD %.8x %.8x\n", offset, mem_mask);
  690          return m_adsp->idma_addr_r();
  691      }
  692      else
  693      {
  694          fatalerror("????\n");
  695          return 0;
  696      }
  697  }
  698  
  699  WRITE32_MEMBER( magictg_state::adsp_idma_addr_w )
  700  {
  701      // TODO: Set /IACK appropriately
  702      if (ACCESSING_BITS_16_31)
  703      {
  704          m_adsp->idma_addr_w(data >> 16);
  705          //mame_printf_debug("WR %.8x %.8x %.8x\n", offset, mem_mask, data >> 16);
  706      }
  707      else
  708          fatalerror("????\n");
  709  }
  710  
  711  READ32_MEMBER( magictg_state::adsp_status_r )
  712  {
  713      // ADSP_IACK = Bit 2
  714      return (0 << 2) | (space.machine().rand() & 1);
  715  }
  716  
  717  READ16_MEMBER( magictg_state::adsp_control_r )
  718  {
  719      UINT16 res = 0;
  720  
  721      switch (offset)
  722      {
  723          case 0x4:
  724              res = m_adsp_regs.bdma_word_count;
  725              break;
  726          case 0x5:
  727              res = space.machine().rand() & 0xff;
  728              break;
  729          default:
  730              mame_printf_debug("Unhandled register: %x\n", 0x3fe0 + offset);
  731      }
  732      return res;
  733  }
  734  
  735  WRITE16_MEMBER( magictg_state::adsp_control_w )
  736  {
  737      switch (offset)
  738      {
  739          case 0x1:
  740              m_adsp_regs.bdma_internal_addr = data & 0x3fff;
  741              break;
  742          case 0x2:
  743              m_adsp_regs.bdma_external_addr = data & 0x3fff;
  744              break;
  745          case 0x3:
  746              m_adsp_regs.bdma_control = data & 0xff0f;
  747              break;
  748          case 0x4:
  749          {
  750              m_adsp_regs.bdma_word_count = data & 0x3fff;
  751  
  752              if (data > 0)
  753              {
  754                  UINT8* adsp_rom = (UINT8*)space.machine().root_device().memregion("adsp")->base();
  755  
  756                  UINT32 page = (m_adsp_regs.bdma_control >> 8) & 0xff;
  757                  UINT32 dir = (m_adsp_regs.bdma_control >> 2) & 1;
  758                  UINT32 type = m_adsp_regs.bdma_control & 3;
  759  
  760                  UINT32 src_addr = (page << 14) | m_adsp_regs.bdma_external_addr;
  761  
  762                  address_space &addr_space = m_adsp->space((type == 0) ? AS_PROGRAM : AS_DATA);
  763  
  764                  if (dir == 0)
  765                  {
  766                      while (m_adsp_regs.bdma_word_count)
  767                      {
  768                          if (type == 0)
  769                          {
  770                              UINT32 src_word =(adsp_rom[src_addr + 0] << 16) |
  771                                                  (adsp_rom[src_addr + 1] << 8) |
  772                                                  (adsp_rom[src_addr + 2]);
  773  
  774                              addr_space.write_dword(m_adsp_regs.bdma_internal_addr * 4, src_word);
  775  
  776                              src_addr += 3;
  777                              m_adsp_regs.bdma_internal_addr ++;
  778                          }
  779                          else if (type == 1)
  780                          {
  781                              UINT32 src_word =(adsp_rom[src_addr + 0] << 8) | adsp_rom[src_addr + 1];
  782  
  783                              addr_space.write_dword(m_adsp_regs.bdma_internal_addr * 2, src_word);
  784  
  785                              src_addr += 2;
  786                              m_adsp_regs.bdma_internal_addr ++;
  787                          }
  788                          else
  789                          {
  790                              fatalerror("Unsupported BDMA width\n");
  791                          }
  792  
  793                          --m_adsp_regs.bdma_word_count;
  794                      }
  795                  }
  796  
  797                  /* Update external address count and page */
  798                  m_adsp_regs.bdma_external_addr = src_addr & 0x3fff;
  799                  m_adsp_regs.bdma_control &= ~0xff00;
  800                  m_adsp_regs.bdma_control |= ((src_addr >> 14) & 0xff) << 8;
  801  
  802                  if (m_adsp_regs.bdma_control & 8)
  803                      m_adsp->set_input_line(INPUT_LINE_RESET, PULSE_LINE);
  804              }
  805              break;
  806          }
  807          case 5:
  808              mame_printf_debug("PFLAGS: %x\n", data);
  809              break;
  810          default:
  811              mame_printf_debug("Unhandled register: %x %x\n", 0x3fe0 + offset, data);
  812      }
  813  }
  814  
  815  
  816  /*************************************
  817   *
  818   *  Main CPU
  819   *
  820   *************************************/
  821  
  822  static ADDRESS_MAP_START( magictg_map, AS_PROGRAM, 32, magictg_state )
  823      AM_RANGE(0x00000000, 0x007fffff) AM_RAM // 8MB RAM
  824      AM_RANGE(0x00800000, 0x0081003f) AM_RAM // ?
  825      AM_RANGE(0x0a000000, 0x0affffff) AM_DEVREADWRITE_LEGACY("voodoo_0", voodoo_r, voodoo_w)
  826  #if defined(USE_TWO_3DFX)
  827      AM_RANGE(0x0b000000, 0x0bffffff) AM_DEVREADWRITE_LEGACY("voodoo_1", voodoo_r, voodoo_w)
  828      AM_RANGE(0x0c000000, 0x0c000fff) AM_READWRITE(zr36120_r, zr36120_w)
  829  #else
  830      AM_RANGE(0x0b000000, 0x0b000fff) AM_READWRITE(zr36120_r, zr36120_w)
  831  #endif
  832      AM_RANGE(0x0f000000, 0x0f000fff) AM_READWRITE(f0_r, f0_w) // Split this up?
  833      AM_RANGE(0x14000100, 0x14000103) AM_READWRITE(adsp_idma_data_r, adsp_idma_data_w)
  834      AM_RANGE(0x14000104, 0x14000107) AM_WRITE(adsp_idma_addr_w)
  835      AM_RANGE(0x1b001024, 0x1b001027) AM_READ(adsp_status_r)
  836      AM_RANGE(0x1b001108, 0x1b00110b) AM_READ(unk_r)
  837      AM_RANGE(0x1e000000, 0x1e002fff) AM_RAM // NVRAM?
  838      AM_RANGE(0x1e800000, 0x1e800007) AM_READWRITE(rand_r, serial_w)
  839      AM_RANGE(0x1fc00000, 0x1fffffff) AM_ROM AM_REGION("mips", 0)
  840  ADDRESS_MAP_END
  841  
  842  
  843  /*************************************
  844   *
  845   *  Mad Cow (IO/sound)
  846   *
  847   *************************************/
  848  
  849  static ADDRESS_MAP_START( adsp_program_map, AS_PROGRAM, 32, magictg_state )
  850      ADDRESS_MAP_UNMAP_HIGH
  851      AM_RANGE(0x0000, 0x3fff) AM_RAM AM_SHARE("adsp_pram")
  852  ADDRESS_MAP_END
  853  
  854  static ADDRESS_MAP_START( adsp_data_map, AS_DATA, 16, magictg_state )
  855      ADDRESS_MAP_UNMAP_HIGH
  856  //  AM_RANGE(0x0000, 0x03ff) AM_RAMBANK("databank")
  857      AM_RANGE(0x0400, 0x3fdf) AM_RAM
  858      AM_RANGE(0x3fe0, 0x3fff) AM_READWRITE(adsp_control_r, adsp_control_w)
  859  ADDRESS_MAP_END
  860  
  861  static ADDRESS_MAP_START( adsp_io_map, AS_IO, 16, magictg_state )
  862      ADDRESS_MAP_UNMAP_HIGH
  863  ADDRESS_MAP_END
  864  
  865  
  866  /*************************************
  867   *
  868   *  Input ports
  869   *
  870   *************************************/
  871  
  872  static INPUT_PORTS_START( magictg )
  873      PORT_START("IPT_TEST")
  874  INPUT_PORTS_END
  875  
  876  
  877  /*************************************
  878   *
  879   *  CPU configuration
  880   *
  881   *************************************/
  882  
  883  /* TODO: Unknown */
  884  static const mips3_config config =
  885  {
  886      16384,              /* code cache size */
  887      16384               /* data cache size */
  888  };
  889  
  890  static const adsp21xx_config adsp_config =
  891  {
  892      NULL,                       /* callback for serial receive */
  893      0,//sound_tx_callback,      /* callback for serial transmit */
  894      0,//timer_enable_callback   /* callback for timer fired */
  895  };
  896  
  897  static const voodoo_config voodoo_1_intf =
  898  {
  899      2, //               fbmem;
  900      4,//                tmumem0;
  901      0,//                tmumem1;
  902      "screen",//         screen;
  903      "mips",//           cputag;
  904      NULL,//             vblank;
  905      NULL,//             stall;
  906  };
  907  
  908  static const voodoo_config voodoo_2_intf =
  909  {
  910      2, //               fbmem;
  911      4,//                tmumem0;
  912      0,//                tmumem1;
  913      "screen",//         screen;
  914      "mips",//           cputag;
  915      NULL,//vblank_assert                vblank;
  916      NULL,// voodoo_stall            stall;
  917  };
  918  /*************************************
  919   *
  920   *  Machine driver
  921   *
  922   *************************************/
  923  
  924  static MACHINE_CONFIG_START( magictg, magictg_state )
  925      MCFG_CPU_ADD("mips", R5000BE, 150000000) /* TODO: CPU type and clock are unknown */
  926      MCFG_CPU_CONFIG(config)
  927      MCFG_CPU_PROGRAM_MAP(magictg_map)
  928  
  929      MCFG_CPU_ADD("adsp", ADSP2181, 16000000)
  930      MCFG_ADSP21XX_CONFIG(adsp_config)
  931      MCFG_CPU_PROGRAM_MAP(adsp_program_map)
  932      MCFG_CPU_DATA_MAP(adsp_data_map)
  933      MCFG_CPU_IO_MAP(adsp_io_map)
  934  
  935      MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
  936  
  937      MCFG_SOUND_ADD("dac1", DMADAC, 0)
  938      MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
  939  
  940      MCFG_SOUND_ADD("dac2", DMADAC, 0)
  941      MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
  942  
  943      MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
  944      MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, pci_dev0_r, pci_dev0_w)
  945      MCFG_PCI_BUS_LEGACY_DEVICE(7, "voodoo_0", voodoo_0_pci_r, voodoo_0_pci_w)
  946  
  947  #if defined(USE_TWO_3DFX)
  948      MCFG_PCI_BUS_LEGACY_DEVICE(8, "voodoo_1", voodoo_1_pci_r, voodoo_1_pci_w)
  949  #endif
  950      MCFG_PCI_BUS_LEGACY_DEVICE(9, "zr36120", zr36120_pci_r, zr36120_pci_w)
  951  
  952      MCFG_3DFX_VOODOO_1_ADD("voodoo_0", STD_VOODOO_1_CLOCK, voodoo_1_intf)
  953  
  954      MCFG_3DFX_VOODOO_1_ADD("voodoo_1", STD_VOODOO_1_CLOCK, voodoo_2_intf)
  955  
  956      MCFG_SCREEN_ADD("screen", RASTER)
  957      MCFG_SCREEN_REFRESH_RATE(60)
  958      MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
  959      MCFG_SCREEN_SIZE(1024, 1024)
  960      MCFG_SCREEN_VISIBLE_AREA(0, 511, 16, 447)
  961  
  962      MCFG_SCREEN_UPDATE_DRIVER(magictg_state, screen_update_magictg)
  963  MACHINE_CONFIG_END
  964  
  965  
  966  /*************************************
  967   *
  968   *  ROM definitions
  969   *
  970   *************************************/
  971  
  972  ROM_START( magictg )
  973      ROM_REGION32_BE( 0x400000, "mips", 0 )
  974      ROM_LOAD16_BYTE( "magic.u34", 0x000000, 0x100000, CRC(2e8971e2) SHA1(9bdf433a7c7257389ebdf131317ef26a7d4e1ba2) )
  975      ROM_LOAD16_BYTE( "magic.u35", 0x000001, 0x100000, CRC(e2202143) SHA1(f07b7da81508cd4594f66e34dabd904a21eb03f0) )
  976      ROM_LOAD16_BYTE( "magic.u32", 0x200000, 0x100000, CRC(f1d530e3) SHA1(fcc392804cd6b98917a869cc5d3826278b7ba90b) )
  977      ROM_LOAD16_BYTE( "magic.u33", 0x200001, 0x100000, CRC(b2330cfc) SHA1(559c35426588b349ef31bf8b296b950912f6fcc7) )
  978  
  979      ROM_REGION16_LE( 0x80000, "adsp", 0 )
  980      ROM_LOAD( "magic.20u", 0x00000, 0x80000, CRC(50968301) SHA1(e9bdd0c942f0c66e18aa8de5a04edb51cdf1fee8) )
  981  
  982      ROM_REGION32_BE( 0x1000000, "adsp_data", 0 )
  983      ROM_LOAD( "magic.snd0.u8", 0x000000, 0x400000, CRC(3cb81717) SHA1(9d35796381ca57e9782e0338c456e63c31d11266) )
  984      ROM_LOAD( "magic.snd1.u14",0x400000, 0x400000, CRC(b4ef9977) SHA1(dedc79e5d506bb0d1649a41b9912dcc999e1da72) )
  985      ROM_LOAD( "magic.snd2.u13",0x800000, 0x400000, CRC(3728f16e) SHA1(6b7da30b100d053e95aa96edf74a0474f1493dfb) )
  986      ROM_LOAD( "magic.snd3.u7", 0xc00000, 0x400000, CRC(11a1cb63) SHA1(a1048d3cd580747c20eb0b4e816e7e4e0f5c8c2b) )
  987  
  988      ROM_REGION( 0x2000000, "jpeg", 0 )
  989      ROM_LOAD( "magic_s0.u9",  0x0000000, 0x800000, CRC(a01b5b99) SHA1(e77f2e9b08a97d6118e1e307b38ea79d0177e9b8) )
  990      ROM_LOAD( "magic_s1.u10", 0x0800000, 0x800000, CRC(d5a1a557) SHA1(2511ee8d08da765a2fa2d42fb504793f9e8b615c) )
  991      ROM_LOAD( "magic_s2.u12", 0x1000000, 0x800000, CRC(06ed6770) SHA1(884a3e4c97a50fa926546eb6def2c11c5732ba88) )
  992      ROM_LOAD( "magic_s3.u11", 0x1800000, 0x800000, CRC(71d4c252) SHA1(aeab2542b9d5fb63f4d60b808010a657a895c1d7) )
  993  
  994      ROM_REGION( 0x400000, "key", 0 )
  995      ROM_LOAD( "magic.k0.u20", 0x000000, 0x400000, CRC(63ab0e9e) SHA1(c4f0b009860ee499496ed7fc1f14ef1e221c1085) )
  996  ROM_END
  997  
  998  ROM_START( magictga )
  999      ROM_REGION32_BE( 0x400000, "mips", 0 )
 1000      ROM_LOAD16_BYTE( "magic.u63", 0x000000, 0x100000, CRC(a10d45f1) SHA1(0ede10f19cf70baf7b43e3f672532b4be1a179f8) )
 1001      ROM_LOAD16_BYTE( "magic.u64", 0x000001, 0x100000, CRC(8fdb6060) SHA1(b638244cad86dc60435a4a9150a5b639f5d61a3f) )
 1002      ROM_LOAD16_BYTE( "magic.u61", 0x200000, 0x100000, CRC(968891d6) SHA1(67ab87039864bb148d20795333ffa7a23e3b84f2) )
 1003      ROM_LOAD16_BYTE( "magic.u62", 0x200001, 0x100000, CRC(690946eb) SHA1(6c9b02367704309f4fde5cbd9d195a45c32c3861) )
 1004  
 1005      // this set was incomplete, none of these roms were dumped for it, are they the same?
 1006      #if 0
 1007      ROM_REGION32_BE( 0x80000, "adsp", 0 )
 1008      ROM_LOAD( "magic.20u", 0x00000, 0x80000, CRC(50968301) SHA1(e9bdd0c942f0c66e18aa8de5a04edb51cdf1fee8) )
 1009  
 1010      ROM_REGION32_BE( 0x1000000, "adsp_data", 0 )
 1011      ROM_LOAD( "magic.snd0.u8", 0x000000, 0x400000, CRC(3cb81717) SHA1(9d35796381ca57e9782e0338c456e63c31d11266) )
 1012      ROM_LOAD( "magic.snd1.u14",0x400000, 0x400000, CRC(b4ef9977) SHA1(dedc79e5d506bb0d1649a41b9912dcc999e1da72) )
 1013      ROM_LOAD( "magic.snd2.u13",0x800000, 0x400000, CRC(3728f16e) SHA1(6b7da30b100d053e95aa96edf74a0474f1493dfb) )
 1014      ROM_LOAD( "magic.snd3.u7", 0xc00000, 0x400000, CRC(11a1cb63) SHA1(a1048d3cd580747c20eb0b4e816e7e4e0f5c8c2b) )
 1015  
 1016      ROM_REGION( 0x2000000, "jpeg", 0 )
 1017      ROM_LOAD( "magic_s0.u9",  0x0000000, 0x800000, CRC(a01b5b99) SHA1(e77f2e9b08a97d6118e1e307b38ea79d0177e9b8) )
 1018      ROM_LOAD( "magic_s1.u10", 0x0800000, 0x800000, CRC(d5a1a557) SHA1(2511ee8d08da765a2fa2d42fb504793f9e8b615c) )
 1019      ROM_LOAD( "magic_s2.u12", 0x1000000, 0x800000, CRC(06ed6770) SHA1(884a3e4c97a50fa926546eb6def2c11c5732ba88) )
 1020      ROM_LOAD( "magic_s3.u11", 0x1800000, 0x800000, CRC(71d4c252) SHA1(aeab2542b9d5fb63f4d60b808010a657a895c1d7) )
 1021  
 1022      ROM_REGION( 0x400000, "key", 0 )
 1023      ROM_LOAD( "magic.k0.u20", 0x000000, 0x400000, CRC(63ab0e9e) SHA1(c4f0b009860ee499496ed7fc1f14ef1e221c1085) )
 1024      #endif
 1025  ROM_END
 1026  
 1027  
 1028  /*************************************
 1029   *
 1030   *  Game driver(s)
 1031   *
 1032   *************************************/
 1033  
 1034  GAME( 1997, magictg,  0,       magictg, magictg, driver_device, 0, ROT0, "Acclaim", "Magic the Gathering: Armageddon (set 1)", GAME_NOT_WORKING | GAME_NO_SOUND )
 1035  GAME( 1997, magictga, magictg, magictg, magictg, driver_device, 0, ROT0, "Acclaim", "Magic the Gathering: Armageddon (set 2)", GAME_NOT_WORKING | GAME_NO_SOUND )